1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
12 #define CONFIG_SYS_FSL_CLK
14 #define CONFIG_DEEP_SLEEP
17 * Size of malloc() pool
19 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
21 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
22 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
25 unsigned long get_board_sys_clk(void);
28 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
29 #define CONFIG_SYS_CLK_FREQ 100000000
30 #define CONFIG_QIXIS_I2C_ACCESS
32 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
36 #define CONFIG_SPL_MAX_SIZE 0x1a000
37 #define CONFIG_SPL_STACK 0x1001d000
38 #define CONFIG_SPL_PAD_TO 0x1c000
40 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
41 CONFIG_SYS_MONITOR_LEN)
42 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
43 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
44 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
45 #define CONFIG_SYS_MONITOR_LEN 0xc0000
48 #ifdef CONFIG_NAND_BOOT
49 #define CONFIG_SPL_MAX_SIZE 0x1a000
50 #define CONFIG_SPL_STACK 0x1001d000
51 #define CONFIG_SPL_PAD_TO 0x1c000
53 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
54 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
55 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
56 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
57 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
59 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
60 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
61 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
62 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
63 #define CONFIG_SYS_MONITOR_LEN 0x80000
66 #define SPD_EEPROM_ADDRESS 0x51
67 #define CONFIG_SYS_SPD_BUS_NUM 0
69 #ifndef CONFIG_SYS_FSL_DDR4
70 #define CONFIG_SYS_DDR_RAW_TIMING
72 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
73 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
75 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
76 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
79 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
85 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
86 #define CONFIG_FSL_IFC
87 #define CONFIG_SYS_FLASH_BASE 0x60000000
88 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
90 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
91 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
95 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
96 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
101 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
103 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
105 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
106 FTIM0_NOR_TEADC(0x5) | \
107 FTIM0_NOR_TEAHC(0x5))
108 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
109 FTIM1_NOR_TRAD_NOR(0x1a) | \
110 FTIM1_NOR_TSEQRAD_NOR(0x13))
111 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
112 FTIM2_NOR_TCH(0x4) | \
113 FTIM2_NOR_TWPH(0xe) | \
115 #define CONFIG_SYS_NOR_FTIM3 0
117 #define CONFIG_SYS_FLASH_QUIET_TEST
118 #define CONFIG_FLASH_SHOW_PROGRESS 45
119 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
120 #define CONFIG_SYS_WRITE_SWAPPED_DATA
122 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
123 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
124 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
125 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
127 #define CONFIG_SYS_FLASH_EMPTY_INFO
128 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
129 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
132 * NAND Flash Definitions
134 #define CONFIG_NAND_FSL_IFC
136 #define CONFIG_SYS_NAND_BASE 0x7e800000
137 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
139 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
141 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
145 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
146 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
147 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
148 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
149 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
150 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
151 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
152 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
154 #define CONFIG_SYS_NAND_ONFI_DETECTION
156 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
157 FTIM0_NAND_TWP(0x18) | \
158 FTIM0_NAND_TWCHT(0x7) | \
160 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
161 FTIM1_NAND_TWBE(0x39) | \
162 FTIM1_NAND_TRR(0xe) | \
163 FTIM1_NAND_TRP(0x18))
164 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
165 FTIM2_NAND_TREH(0xa) | \
166 FTIM2_NAND_TWHRE(0x1e))
167 #define CONFIG_SYS_NAND_FTIM3 0x0
169 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
170 #define CONFIG_SYS_MAX_NAND_DEVICE 1
172 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
178 #define CONFIG_FSL_QIXIS
180 #ifdef CONFIG_FSL_QIXIS
181 #define QIXIS_BASE 0x7fb00000
182 #define QIXIS_BASE_PHYS QIXIS_BASE
183 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
184 #define QIXIS_LBMAP_SWITCH 6
185 #define QIXIS_LBMAP_MASK 0x0f
186 #define QIXIS_LBMAP_SHIFT 0
187 #define QIXIS_LBMAP_DFLTBANK 0x00
188 #define QIXIS_LBMAP_ALTBANK 0x04
189 #define QIXIS_PWR_CTL 0x21
190 #define QIXIS_PWR_CTL_POWEROFF 0x80
191 #define QIXIS_RST_CTL_RESET 0x44
192 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
193 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
194 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
195 #define QIXIS_CTL_SYS 0x5
196 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
197 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
198 #define QIXIS_RST_FORCE_3 0x45
199 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
200 #define QIXIS_PWR_CTL2 0x21
201 #define QIXIS_PWR_CTL2_PCTL 0x2
203 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
204 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
208 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
209 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
210 CSOR_NOR_NOR_MODE_AVD_NOR | \
214 * QIXIS Timing parameters for IFC GPCM
216 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
217 FTIM0_GPCM_TEADC(0xe) | \
218 FTIM0_GPCM_TEAHC(0xe))
219 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
220 FTIM1_GPCM_TRAD(0x1f))
221 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
222 FTIM2_GPCM_TCH(0xe) | \
223 FTIM2_GPCM_TWP(0xf0))
224 #define CONFIG_SYS_FPGA_FTIM3 0x0
227 #if defined(CONFIG_NAND_BOOT)
228 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
229 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
230 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
231 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
232 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
233 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
234 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
235 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
236 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
237 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
238 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
239 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
240 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
241 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
242 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
243 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
244 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
245 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
246 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
247 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
248 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
249 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
250 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
251 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
252 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
253 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
254 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
255 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
256 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
257 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
258 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
259 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
261 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
262 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
263 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
264 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
265 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
266 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
267 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
268 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
269 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
270 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
271 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
272 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
273 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
274 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
275 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
276 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
277 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
278 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
279 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
280 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
281 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
282 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
283 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
284 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
285 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
286 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
287 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
288 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
289 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
290 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
291 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
292 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
299 #define CONFIG_LPUART_32B_REG
301 #define CONFIG_SYS_NS16550_SERIAL
302 #ifndef CONFIG_DM_SERIAL
303 #define CONFIG_SYS_NS16550_REG_SIZE 1
305 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
313 #ifdef CONFIG_DM_GPIO
314 #ifndef CONFIG_MPC8XXX_GPIO
315 #define CONFIG_MPC8XXX_GPIO
320 #define CONFIG_SYS_I2C_EEPROM_NXID
321 #define CONFIG_SYS_EEPROM_BUS_NUM 0
324 * I2C bus multiplexer
326 #define I2C_MUX_PCA_ADDR_PRI 0x77
327 #define I2C_MUX_CH_DEFAULT 0x8
328 #define I2C_MUX_CH_CH7301 0xC
337 #ifdef CONFIG_VIDEO_FSL_DCU_FB
338 #define CONFIG_VIDEO_LOGO
339 #define CONFIG_VIDEO_BMP_LOGO
341 #define CONFIG_FSL_DIU_CH7301
342 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
343 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
344 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
351 #ifdef CONFIG_TSEC_ENET
352 #define CONFIG_MII_DEFAULT_TSEC 3
353 #define CONFIG_TSEC1 1
354 #define CONFIG_TSEC1_NAME "eTSEC1"
355 #define CONFIG_TSEC2 1
356 #define CONFIG_TSEC2_NAME "eTSEC2"
357 #define CONFIG_TSEC3 1
358 #define CONFIG_TSEC3_NAME "eTSEC3"
360 #define TSEC1_PHY_ADDR 1
361 #define TSEC2_PHY_ADDR 2
362 #define TSEC3_PHY_ADDR 3
364 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
365 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
366 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
368 #define TSEC1_PHYIDX 0
369 #define TSEC2_PHYIDX 0
370 #define TSEC3_PHYIDX 0
372 #define CONFIG_ETHPRIME "eTSEC1"
374 #define CONFIG_HAS_ETH0
375 #define CONFIG_HAS_ETH1
376 #define CONFIG_HAS_ETH2
378 #define CONFIG_FSL_SGMII_RISER 1
379 #define SGMII_RISER_PHY_OFFSET 0x1b
381 #ifdef CONFIG_FSL_SGMII_RISER
382 #define CONFIG_SYS_TBIPA_VALUE 8
388 #define CONFIG_PCIE1 /* PCIE controller 1 */
389 #define CONFIG_PCIE2 /* PCIE controller 2 */
392 #define CONFIG_PCI_SCAN_SHOW
395 #define CONFIG_CMDLINE_TAG
397 #define CONFIG_PEN_ADDR_BIG_ENDIAN
398 #define CONFIG_LAYERSCAPE_NS_ACCESS
399 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
400 #define COUNTER_FREQUENCY 12500000
402 #define CONFIG_HWCONFIG
403 #define HWCONFIG_BUFFER_SIZE 256
405 #define CONFIG_FSL_DEVICE_DISABLE
408 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
411 #define CONFIG_EXTRA_ENV_SETTINGS \
412 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
413 "initrd_high=0xffffffff\0" \
414 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
416 #define CONFIG_EXTRA_ENV_SETTINGS \
417 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
418 "initrd_high=0xffffffff\0" \
419 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
423 * Miscellaneous configurable options
425 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
427 #define CONFIG_LS102XA_STREAM_ID
429 #define CONFIG_SYS_INIT_SP_OFFSET \
430 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
431 #define CONFIG_SYS_INIT_SP_ADDR \
432 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
434 #ifdef CONFIG_SPL_BUILD
435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
437 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
444 #include <asm/fsl_secure_boot.h>
445 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */