include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #ifdef CONFIG_SD_BOOT
  14 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  15                 CONFIG_SYS_MONITOR_LEN)
  16 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  17 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  18 #endif
  19
  20 #ifdef CONFIG_NAND_BOOT
  21 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  22 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  23 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  24
  25 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  26 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  27 #define CONFIG_SYS_MONITOR_LEN          0x80000
  28 #endif
  29
  30 #define SPD_EEPROM_ADDRESS              0x51
  31 #define CONFIG_SYS_SPD_BUS_NUM          0
  32
  33 #ifndef CONFIG_SYS_FSL_DDR4
  34 #define CONFIG_SYS_DDR_RAW_TIMING
  35 #endif
  36
  37 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  38 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  39
  40 #ifdef CONFIG_DDR_ECC
  41 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  42 #endif
  43
  44 /*
  45  * IFC Definitions
  46  */
  47 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  48 #define CONFIG_SYS_FLASH_BASE           0x60000000
  49 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  50
  51 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  52 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  53                                 CSPR_PORT_SIZE_16 | \
  54                                 CSPR_MSEL_NOR | \
  55                                 CSPR_V)
  56 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  57 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  58                                 + 0x8000000) | \
  59                                 CSPR_PORT_SIZE_16 | \
  60                                 CSPR_MSEL_NOR | \
  61                                 CSPR_V)
  62 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  63
  64 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  65                                         CSOR_NOR_TRHZ_80)
  66 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  67                                         FTIM0_NOR_TEADC(0x5) | \
  68                                         FTIM0_NOR_TEAHC(0x5))
  69 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  70                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  71                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  72 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  73                                         FTIM2_NOR_TCH(0x4) | \
  74                                         FTIM2_NOR_TWPH(0xe) | \
  75                                         FTIM2_NOR_TWP(0x1c))
  76 #define CONFIG_SYS_NOR_FTIM3            0
  77
  78 #define CONFIG_SYS_FLASH_QUIET_TEST
  79 #define CONFIG_FLASH_SHOW_PROGRESS      45
  80 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  81
  82 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  83 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  84 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  85
  86 #define CONFIG_SYS_FLASH_EMPTY_INFO
  87 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  88                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  89
  90 /*
  91  * NAND Flash Definitions
  92  */
  93
  94 #define CONFIG_SYS_NAND_BASE            0x7e800000
  95 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  96
  97 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  98
  99 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 100                                 | CSPR_PORT_SIZE_8      \
 101                                 | CSPR_MSEL_NAND        \
 102                                 | CSPR_V)
 103 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 104 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 105                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 106                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 107                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 108                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 109                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 110                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 111
 112 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 113                                         FTIM0_NAND_TWP(0x18)   | \
 114                                         FTIM0_NAND_TWCHT(0x7) | \
 115                                         FTIM0_NAND_TWH(0xa))
 116 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 117                                         FTIM1_NAND_TWBE(0x39)  | \
 118                                         FTIM1_NAND_TRR(0xe)   | \
 119                                         FTIM1_NAND_TRP(0x18))
 120 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 121                                         FTIM2_NAND_TREH(0xa) | \
 122                                         FTIM2_NAND_TWHRE(0x1e))
 123 #define CONFIG_SYS_NAND_FTIM3           0x0
 124
 125 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 126 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 127 #endif
 128
 129 /*
 130  * QIXIS Definitions
 131  */
 132
 133 #ifdef CONFIG_FSL_QIXIS
 134 #define QIXIS_BASE                      0x7fb00000
 135 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 136 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 137 #define QIXIS_LBMAP_SWITCH              6
 138 #define QIXIS_LBMAP_MASK                0x0f
 139 #define QIXIS_LBMAP_SHIFT               0
 140 #define QIXIS_LBMAP_DFLTBANK            0x00
 141 #define QIXIS_LBMAP_ALTBANK             0x04
 142 #define QIXIS_PWR_CTL                   0x21
 143 #define QIXIS_PWR_CTL_POWEROFF          0x80
 144 #define QIXIS_RST_CTL_RESET             0x44
 145 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 146 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 147 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 148 #define QIXIS_CTL_SYS                   0x5
 149 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 150 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 151 #define QIXIS_RST_FORCE_3               0x45
 152 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 153 #define QIXIS_PWR_CTL2                  0x21
 154 #define QIXIS_PWR_CTL2_PCTL             0x2
 155
 156 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 157 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 158                                         CSPR_PORT_SIZE_8 | \
 159                                         CSPR_MSEL_GPCM | \
 160                                         CSPR_V)
 161 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 162 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 163                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 164                                         CSOR_NOR_TRHZ_80)
 165
 166 /*
 167  * QIXIS Timing parameters for IFC GPCM
 168  */
 169 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 170                                         FTIM0_GPCM_TEADC(0xe) | \
 171                                         FTIM0_GPCM_TEAHC(0xe))
 172 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 173                                         FTIM1_GPCM_TRAD(0x1f))
 174 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 175                                         FTIM2_GPCM_TCH(0xe) | \
 176                                         FTIM2_GPCM_TWP(0xf0))
 177 #define CONFIG_SYS_FPGA_FTIM3           0x0
 178 #endif
 179
 180 #if defined(CONFIG_NAND_BOOT)
 181 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 182 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 183 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 184 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 185 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 186 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 187 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 188 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 189 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 190 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 191 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 192 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 193 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 194 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 195 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 196 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 197 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 198 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 199 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 200 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 201 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 202 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 203 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 204 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 205 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 206 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 207 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 208 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 209 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 210 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 211 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 212 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 213 #else
 214 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 215 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 216 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 217 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 218 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 219 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 220 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 221 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 222 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 223 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 224 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 225 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 226 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 227 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 228 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 229 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 230 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 231 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 232 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 233 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 234 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 235 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 236 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 237 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 238 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 239 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 240 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 241 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 242 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 243 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 244 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 245 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 246 #endif
 247
 248 /*
 249  * Serial Port
 250  */
 251 #ifndef CONFIG_LPUART
 252 #define CONFIG_SYS_NS16550_SERIAL
 253 #ifndef CONFIG_DM_SERIAL
 254 #define CONFIG_SYS_NS16550_REG_SIZE     1
 255 #endif
 256 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 257 #endif
 258
 259 /*
 260  * I2C
 261  */
 262
 263 /* GPIO */
 264
 265 /* EEPROM */
 266 #define CONFIG_SYS_I2C_EEPROM_NXID
 267 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 268
 269 /*
 270  * I2C bus multiplexer
 271  */
 272 #define I2C_MUX_PCA_ADDR_PRI            0x77
 273 #define I2C_MUX_CH_DEFAULT              0x8
 274 #define I2C_MUX_CH_CH7301               0xC
 275
 276 /*
 277  * MMC
 278  */
 279
 280 /*
 281  * eTSEC
 282  */
 283
 284 #ifdef CONFIG_TSEC_ENET
 285 #define CONFIG_MII_DEFAULT_TSEC         3
 286 #define CONFIG_TSEC1                    1
 287 #define CONFIG_TSEC1_NAME               "eTSEC1"
 288 #define CONFIG_TSEC2                    1
 289 #define CONFIG_TSEC2_NAME               "eTSEC2"
 290 #define CONFIG_TSEC3                    1
 291 #define CONFIG_TSEC3_NAME               "eTSEC3"
 292
 293 #define TSEC1_PHY_ADDR                  1
 294 #define TSEC2_PHY_ADDR                  2
 295 #define TSEC3_PHY_ADDR                  3
 296
 297 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 298 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 299 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 300
 301 #define TSEC1_PHYIDX                    0
 302 #define TSEC2_PHYIDX                    0
 303 #define TSEC3_PHYIDX                    0
 304
 305 #define CONFIG_FSL_SGMII_RISER          1
 306 #define SGMII_RISER_PHY_OFFSET          0x1b
 307
 308 #ifdef CONFIG_FSL_SGMII_RISER
 309 #define CONFIG_SYS_TBIPA_VALUE          8
 310 #endif
 311
 312 #endif
 313
 314 /* PCIe */
 315 #define CONFIG_PCIE1            /* PCIE controller 1 */
 316 #define CONFIG_PCIE2            /* PCIE controller 2 */
 317
 318 #ifdef CONFIG_PCI
 319 #define CONFIG_PCI_SCAN_SHOW
 320 #endif
 321
 322 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 323 #define CONFIG_LAYERSCAPE_NS_ACCESS
 324 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 325
 326 #define CONFIG_HWCONFIG
 327 #define HWCONFIG_BUFFER_SIZE            256
 328
 329 #define CONFIG_FSL_DEVICE_DISABLE
 330
 331 #ifdef CONFIG_LPUART
 332 #define CONFIG_EXTRA_ENV_SETTINGS       \
 333         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 334         "initrd_high=0xffffffff\0"      \
 335         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 336 #else
 337 #define CONFIG_EXTRA_ENV_SETTINGS       \
 338         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 339         "initrd_high=0xffffffff\0"      \
 340         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 341 #endif
 342
 343 /*
 344  * Miscellaneous configurable options
 345  */
 346 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 347
 348 #define CONFIG_LS102XA_STREAM_ID
 349
 350 /*
 351  * Environment
 352  */
 353
 354 #include <asm/fsl_secure_boot.h>
 355 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 356
 357 #endif