include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #ifdef CONFIG_SD_BOOT
  14 #define CONFIG_SPL_STACK                0x1001d000
  15
  16 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  17                 CONFIG_SYS_MONITOR_LEN)
  18 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  19 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  20 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  21 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  22 #endif
  23
  24 #ifdef CONFIG_NAND_BOOT
  25 #define CONFIG_SPL_STACK                0x1001d000
  26
  27 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  28 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  29 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  30
  31 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  32 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  33 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  34 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  35 #define CONFIG_SYS_MONITOR_LEN          0x80000
  36 #endif
  37
  38 #define SPD_EEPROM_ADDRESS              0x51
  39 #define CONFIG_SYS_SPD_BUS_NUM          0
  40
  41 #ifndef CONFIG_SYS_FSL_DDR4
  42 #define CONFIG_SYS_DDR_RAW_TIMING
  43 #endif
  44
  45 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  46 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  47
  48 #ifdef CONFIG_DDR_ECC
  49 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  50 #endif
  51
  52 /*
  53  * IFC Definitions
  54  */
  55 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  56 #define CONFIG_SYS_FLASH_BASE           0x60000000
  57 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  58
  59 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  60 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  61                                 CSPR_PORT_SIZE_16 | \
  62                                 CSPR_MSEL_NOR | \
  63                                 CSPR_V)
  64 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  65 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  66                                 + 0x8000000) | \
  67                                 CSPR_PORT_SIZE_16 | \
  68                                 CSPR_MSEL_NOR | \
  69                                 CSPR_V)
  70 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  71
  72 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  73                                         CSOR_NOR_TRHZ_80)
  74 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  75                                         FTIM0_NOR_TEADC(0x5) | \
  76                                         FTIM0_NOR_TEAHC(0x5))
  77 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  78                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  79                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  80 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  81                                         FTIM2_NOR_TCH(0x4) | \
  82                                         FTIM2_NOR_TWPH(0xe) | \
  83                                         FTIM2_NOR_TWP(0x1c))
  84 #define CONFIG_SYS_NOR_FTIM3            0
  85
  86 #define CONFIG_SYS_FLASH_QUIET_TEST
  87 #define CONFIG_FLASH_SHOW_PROGRESS      45
  88 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  89
  90 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  91 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  92 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  93
  94 #define CONFIG_SYS_FLASH_EMPTY_INFO
  95 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  96                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  97
  98 /*
  99  * NAND Flash Definitions
 100  */
 101
 102 #define CONFIG_SYS_NAND_BASE            0x7e800000
 103 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 104
 105 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 106
 107 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 108                                 | CSPR_PORT_SIZE_8      \
 109                                 | CSPR_MSEL_NAND        \
 110                                 | CSPR_V)
 111 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 112 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 113                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 114                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 115                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 116                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 117                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 118                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 119
 120 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 121                                         FTIM0_NAND_TWP(0x18)   | \
 122                                         FTIM0_NAND_TWCHT(0x7) | \
 123                                         FTIM0_NAND_TWH(0xa))
 124 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 125                                         FTIM1_NAND_TWBE(0x39)  | \
 126                                         FTIM1_NAND_TRR(0xe)   | \
 127                                         FTIM1_NAND_TRP(0x18))
 128 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 129                                         FTIM2_NAND_TREH(0xa) | \
 130                                         FTIM2_NAND_TWHRE(0x1e))
 131 #define CONFIG_SYS_NAND_FTIM3           0x0
 132
 133 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 134 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 135 #endif
 136
 137 /*
 138  * QIXIS Definitions
 139  */
 140
 141 #ifdef CONFIG_FSL_QIXIS
 142 #define QIXIS_BASE                      0x7fb00000
 143 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 144 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 145 #define QIXIS_LBMAP_SWITCH              6
 146 #define QIXIS_LBMAP_MASK                0x0f
 147 #define QIXIS_LBMAP_SHIFT               0
 148 #define QIXIS_LBMAP_DFLTBANK            0x00
 149 #define QIXIS_LBMAP_ALTBANK             0x04
 150 #define QIXIS_PWR_CTL                   0x21
 151 #define QIXIS_PWR_CTL_POWEROFF          0x80
 152 #define QIXIS_RST_CTL_RESET             0x44
 153 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 154 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 155 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 156 #define QIXIS_CTL_SYS                   0x5
 157 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 158 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 159 #define QIXIS_RST_FORCE_3               0x45
 160 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 161 #define QIXIS_PWR_CTL2                  0x21
 162 #define QIXIS_PWR_CTL2_PCTL             0x2
 163
 164 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 165 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 166                                         CSPR_PORT_SIZE_8 | \
 167                                         CSPR_MSEL_GPCM | \
 168                                         CSPR_V)
 169 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 170 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 171                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 172                                         CSOR_NOR_TRHZ_80)
 173
 174 /*
 175  * QIXIS Timing parameters for IFC GPCM
 176  */
 177 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 178                                         FTIM0_GPCM_TEADC(0xe) | \
 179                                         FTIM0_GPCM_TEAHC(0xe))
 180 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 181                                         FTIM1_GPCM_TRAD(0x1f))
 182 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 183                                         FTIM2_GPCM_TCH(0xe) | \
 184                                         FTIM2_GPCM_TWP(0xf0))
 185 #define CONFIG_SYS_FPGA_FTIM3           0x0
 186 #endif
 187
 188 #if defined(CONFIG_NAND_BOOT)
 189 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 190 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 191 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 192 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 193 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 194 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 195 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 196 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 197 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 198 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 199 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 200 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 201 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 202 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 203 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 204 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 205 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 206 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 207 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 208 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 209 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 210 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 211 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 212 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 213 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 214 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 215 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 216 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 217 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 218 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 219 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 220 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 221 #else
 222 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 223 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 224 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 225 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 226 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 227 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 228 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 229 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 230 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 231 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 232 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 233 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 234 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 235 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 236 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 237 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 238 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 239 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 240 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 241 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 242 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 243 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 244 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 245 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 246 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 247 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 248 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 249 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 250 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 251 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 252 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 253 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 254 #endif
 255
 256 /*
 257  * Serial Port
 258  */
 259 #ifndef CONFIG_LPUART
 260 #define CONFIG_SYS_NS16550_SERIAL
 261 #ifndef CONFIG_DM_SERIAL
 262 #define CONFIG_SYS_NS16550_REG_SIZE     1
 263 #endif
 264 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 265 #endif
 266
 267 /*
 268  * I2C
 269  */
 270
 271 /* GPIO */
 272
 273 /* EEPROM */
 274 #define CONFIG_SYS_I2C_EEPROM_NXID
 275 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 276
 277 /*
 278  * I2C bus multiplexer
 279  */
 280 #define I2C_MUX_PCA_ADDR_PRI            0x77
 281 #define I2C_MUX_CH_DEFAULT              0x8
 282 #define I2C_MUX_CH_CH7301               0xC
 283
 284 /*
 285  * MMC
 286  */
 287
 288 /*
 289  * eTSEC
 290  */
 291
 292 #ifdef CONFIG_TSEC_ENET
 293 #define CONFIG_MII_DEFAULT_TSEC         3
 294 #define CONFIG_TSEC1                    1
 295 #define CONFIG_TSEC1_NAME               "eTSEC1"
 296 #define CONFIG_TSEC2                    1
 297 #define CONFIG_TSEC2_NAME               "eTSEC2"
 298 #define CONFIG_TSEC3                    1
 299 #define CONFIG_TSEC3_NAME               "eTSEC3"
 300
 301 #define TSEC1_PHY_ADDR                  1
 302 #define TSEC2_PHY_ADDR                  2
 303 #define TSEC3_PHY_ADDR                  3
 304
 305 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 306 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 307 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 308
 309 #define TSEC1_PHYIDX                    0
 310 #define TSEC2_PHYIDX                    0
 311 #define TSEC3_PHYIDX                    0
 312
 313 #define CONFIG_FSL_SGMII_RISER          1
 314 #define SGMII_RISER_PHY_OFFSET          0x1b
 315
 316 #ifdef CONFIG_FSL_SGMII_RISER
 317 #define CONFIG_SYS_TBIPA_VALUE          8
 318 #endif
 319
 320 #endif
 321
 322 /* PCIe */
 323 #define CONFIG_PCIE1            /* PCIE controller 1 */
 324 #define CONFIG_PCIE2            /* PCIE controller 2 */
 325
 326 #ifdef CONFIG_PCI
 327 #define CONFIG_PCI_SCAN_SHOW
 328 #endif
 329
 330 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 331 #define CONFIG_LAYERSCAPE_NS_ACCESS
 332 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 333
 334 #define CONFIG_HWCONFIG
 335 #define HWCONFIG_BUFFER_SIZE            256
 336
 337 #define CONFIG_FSL_DEVICE_DISABLE
 338
 339 #ifdef CONFIG_LPUART
 340 #define CONFIG_EXTRA_ENV_SETTINGS       \
 341         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 342         "initrd_high=0xffffffff\0"      \
 343         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 344 #else
 345 #define CONFIG_EXTRA_ENV_SETTINGS       \
 346         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 347         "initrd_high=0xffffffff\0"      \
 348         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 349 #endif
 350
 351 /*
 352  * Miscellaneous configurable options
 353  */
 354 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 355
 356 #define CONFIG_LS102XA_STREAM_ID
 357
 358 #define CONFIG_SYS_INIT_SP_OFFSET \
 359         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 360 #define CONFIG_SYS_INIT_SP_ADDR \
 361         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 362
 363 /*
 364  * Environment
 365  */
 366
 367 #include <asm/fsl_secure_boot.h>
 368 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 369
 370 #endif