include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 #define CONFIG_DEEP_SLEEP
  15
  16 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  17 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  18
  19 #ifndef __ASSEMBLY__
  20 unsigned long get_board_sys_clk(void);
  21 #endif
  22
  23 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  24 #define CONFIG_SYS_CLK_FREQ             100000000
  25 #define CONFIG_QIXIS_I2C_ACCESS
  26 #else
  27 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  28 #endif
  29
  30 #ifdef CONFIG_SD_BOOT
  31 #define CONFIG_SPL_MAX_SIZE             0x1a000
  32 #define CONFIG_SPL_STACK                0x1001d000
  33 #define CONFIG_SPL_PAD_TO               0x1c000
  34
  35 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  36                 CONFIG_SYS_MONITOR_LEN)
  37 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  38 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  39 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  40 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  41 #endif
  42
  43 #ifdef CONFIG_NAND_BOOT
  44 #define CONFIG_SPL_MAX_SIZE             0x1a000
  45 #define CONFIG_SPL_STACK                0x1001d000
  46 #define CONFIG_SPL_PAD_TO               0x1c000
  47
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
  50 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  51 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  52 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  53
  54 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  55 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  56 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  57 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  58 #define CONFIG_SYS_MONITOR_LEN          0x80000
  59 #endif
  60
  61 #define SPD_EEPROM_ADDRESS              0x51
  62 #define CONFIG_SYS_SPD_BUS_NUM          0
  63
  64 #ifndef CONFIG_SYS_FSL_DDR4
  65 #define CONFIG_SYS_DDR_RAW_TIMING
  66 #endif
  67 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  68 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  69
  70 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  71 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  72
  73 #ifdef CONFIG_DDR_ECC
  74 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  75 #endif
  76
  77 /*
  78  * IFC Definitions
  79  */
  80 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  81 #define CONFIG_FSL_IFC
  82 #define CONFIG_SYS_FLASH_BASE           0x60000000
  83 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  84
  85 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  86 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  87                                 CSPR_PORT_SIZE_16 | \
  88                                 CSPR_MSEL_NOR | \
  89                                 CSPR_V)
  90 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  91 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  92                                 + 0x8000000) | \
  93                                 CSPR_PORT_SIZE_16 | \
  94                                 CSPR_MSEL_NOR | \
  95                                 CSPR_V)
  96 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  97
  98 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  99                                         CSOR_NOR_TRHZ_80)
 100 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 101                                         FTIM0_NOR_TEADC(0x5) | \
 102                                         FTIM0_NOR_TEAHC(0x5))
 103 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 104                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 105                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 106 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 107                                         FTIM2_NOR_TCH(0x4) | \
 108                                         FTIM2_NOR_TWPH(0xe) | \
 109                                         FTIM2_NOR_TWP(0x1c))
 110 #define CONFIG_SYS_NOR_FTIM3            0
 111
 112 #define CONFIG_SYS_FLASH_QUIET_TEST
 113 #define CONFIG_FLASH_SHOW_PROGRESS      45
 114 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 115 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 116
 117 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 118 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 119 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 120 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 121
 122 #define CONFIG_SYS_FLASH_EMPTY_INFO
 123 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 124                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 125
 126 /*
 127  * NAND Flash Definitions
 128  */
 129 #define CONFIG_NAND_FSL_IFC
 130
 131 #define CONFIG_SYS_NAND_BASE            0x7e800000
 132 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 133
 134 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 135
 136 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 137                                 | CSPR_PORT_SIZE_8      \
 138                                 | CSPR_MSEL_NAND        \
 139                                 | CSPR_V)
 140 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 141 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 142                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 143                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 144                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 145                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 146                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 147                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 148
 149 #define CONFIG_SYS_NAND_ONFI_DETECTION
 150
 151 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 152                                         FTIM0_NAND_TWP(0x18)   | \
 153                                         FTIM0_NAND_TWCHT(0x7) | \
 154                                         FTIM0_NAND_TWH(0xa))
 155 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 156                                         FTIM1_NAND_TWBE(0x39)  | \
 157                                         FTIM1_NAND_TRR(0xe)   | \
 158                                         FTIM1_NAND_TRP(0x18))
 159 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 160                                         FTIM2_NAND_TREH(0xa) | \
 161                                         FTIM2_NAND_TWHRE(0x1e))
 162 #define CONFIG_SYS_NAND_FTIM3           0x0
 163
 164 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 165 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 166
 167 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 168 #endif
 169
 170 /*
 171  * QIXIS Definitions
 172  */
 173 #define CONFIG_FSL_QIXIS
 174
 175 #ifdef CONFIG_FSL_QIXIS
 176 #define QIXIS_BASE                      0x7fb00000
 177 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 178 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 179 #define QIXIS_LBMAP_SWITCH              6
 180 #define QIXIS_LBMAP_MASK                0x0f
 181 #define QIXIS_LBMAP_SHIFT               0
 182 #define QIXIS_LBMAP_DFLTBANK            0x00
 183 #define QIXIS_LBMAP_ALTBANK             0x04
 184 #define QIXIS_PWR_CTL                   0x21
 185 #define QIXIS_PWR_CTL_POWEROFF          0x80
 186 #define QIXIS_RST_CTL_RESET             0x44
 187 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 188 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 189 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 190 #define QIXIS_CTL_SYS                   0x5
 191 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 192 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 193 #define QIXIS_RST_FORCE_3               0x45
 194 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 195 #define QIXIS_PWR_CTL2                  0x21
 196 #define QIXIS_PWR_CTL2_PCTL             0x2
 197
 198 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 199 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 200                                         CSPR_PORT_SIZE_8 | \
 201                                         CSPR_MSEL_GPCM | \
 202                                         CSPR_V)
 203 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 204 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 205                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 206                                         CSOR_NOR_TRHZ_80)
 207
 208 /*
 209  * QIXIS Timing parameters for IFC GPCM
 210  */
 211 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 212                                         FTIM0_GPCM_TEADC(0xe) | \
 213                                         FTIM0_GPCM_TEAHC(0xe))
 214 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 215                                         FTIM1_GPCM_TRAD(0x1f))
 216 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 217                                         FTIM2_GPCM_TCH(0xe) | \
 218                                         FTIM2_GPCM_TWP(0xf0))
 219 #define CONFIG_SYS_FPGA_FTIM3           0x0
 220 #endif
 221
 222 #if defined(CONFIG_NAND_BOOT)
 223 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 224 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 225 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 226 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 227 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 228 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 229 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 230 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 231 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 232 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 233 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 234 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 235 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 236 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 237 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 238 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 239 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 240 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 241 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 242 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 243 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 244 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 245 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 246 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 247 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 248 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 249 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 250 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 251 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 252 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 253 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 254 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 255 #else
 256 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 257 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 258 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 259 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 260 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 261 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 262 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 263 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 264 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 265 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 266 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 267 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 268 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 269 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 270 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 271 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 272 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 273 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 274 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 275 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 276 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 277 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 278 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 279 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 280 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 281 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 282 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 283 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 284 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 285 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 286 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 287 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 288 #endif
 289
 290 /*
 291  * Serial Port
 292  */
 293 #ifdef CONFIG_LPUART
 294 #define CONFIG_LPUART_32B_REG
 295 #else
 296 #define CONFIG_SYS_NS16550_SERIAL
 297 #ifndef CONFIG_DM_SERIAL
 298 #define CONFIG_SYS_NS16550_REG_SIZE     1
 299 #endif
 300 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 301 #endif
 302
 303 /*
 304  * I2C
 305  */
 306
 307 /* GPIO */
 308 #ifdef CONFIG_DM_GPIO
 309 #ifndef CONFIG_MPC8XXX_GPIO
 310 #define CONFIG_MPC8XXX_GPIO
 311 #endif
 312 #endif
 313
 314 /* EEPROM */
 315 #define CONFIG_SYS_I2C_EEPROM_NXID
 316 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 317
 318 /*
 319  * I2C bus multiplexer
 320  */
 321 #define I2C_MUX_PCA_ADDR_PRI            0x77
 322 #define I2C_MUX_CH_DEFAULT              0x8
 323 #define I2C_MUX_CH_CH7301               0xC
 324
 325 /*
 326  * MMC
 327  */
 328
 329 /*
 330  * Video
 331  */
 332 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 333 #define CONFIG_VIDEO_LOGO
 334 #define CONFIG_VIDEO_BMP_LOGO
 335
 336 #define CONFIG_FSL_DIU_CH7301
 337 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 338 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 339 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 340 #endif
 341
 342 /*
 343  * eTSEC
 344  */
 345
 346 #ifdef CONFIG_TSEC_ENET
 347 #define CONFIG_MII_DEFAULT_TSEC         3
 348 #define CONFIG_TSEC1                    1
 349 #define CONFIG_TSEC1_NAME               "eTSEC1"
 350 #define CONFIG_TSEC2                    1
 351 #define CONFIG_TSEC2_NAME               "eTSEC2"
 352 #define CONFIG_TSEC3                    1
 353 #define CONFIG_TSEC3_NAME               "eTSEC3"
 354
 355 #define TSEC1_PHY_ADDR                  1
 356 #define TSEC2_PHY_ADDR                  2
 357 #define TSEC3_PHY_ADDR                  3
 358
 359 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 360 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 361 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 362
 363 #define TSEC1_PHYIDX                    0
 364 #define TSEC2_PHYIDX                    0
 365 #define TSEC3_PHYIDX                    0
 366
 367 #define CONFIG_ETHPRIME                 "eTSEC1"
 368
 369 #define CONFIG_HAS_ETH0
 370 #define CONFIG_HAS_ETH1
 371 #define CONFIG_HAS_ETH2
 372
 373 #define CONFIG_FSL_SGMII_RISER          1
 374 #define SGMII_RISER_PHY_OFFSET          0x1b
 375
 376 #ifdef CONFIG_FSL_SGMII_RISER
 377 #define CONFIG_SYS_TBIPA_VALUE          8
 378 #endif
 379
 380 #endif
 381
 382 /* PCIe */
 383 #define CONFIG_PCIE1            /* PCIE controller 1 */
 384 #define CONFIG_PCIE2            /* PCIE controller 2 */
 385
 386 #ifdef CONFIG_PCI
 387 #define CONFIG_PCI_SCAN_SHOW
 388 #endif
 389
 390 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 391 #define CONFIG_LAYERSCAPE_NS_ACCESS
 392 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 393 #define COUNTER_FREQUENCY               12500000
 394
 395 #define CONFIG_HWCONFIG
 396 #define HWCONFIG_BUFFER_SIZE            256
 397
 398 #define CONFIG_FSL_DEVICE_DISABLE
 399
 400
 401 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 402
 403 #ifdef CONFIG_LPUART
 404 #define CONFIG_EXTRA_ENV_SETTINGS       \
 405         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 406         "initrd_high=0xffffffff\0"      \
 407         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 408 #else
 409 #define CONFIG_EXTRA_ENV_SETTINGS       \
 410         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 411         "initrd_high=0xffffffff\0"      \
 412         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 413 #endif
 414
 415 /*
 416  * Miscellaneous configurable options
 417  */
 418 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 419
 420 #define CONFIG_LS102XA_STREAM_ID
 421
 422 #define CONFIG_SYS_INIT_SP_OFFSET \
 423         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 424 #define CONFIG_SYS_INIT_SP_ADDR \
 425         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 426
 427 #ifdef CONFIG_SPL_BUILD
 428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 429 #else
 430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 431 #endif
 432
 433 /*
 434  * Environment
 435  */
 436
 437 #include <asm/fsl_secure_boot.h>
 438 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 439
 440 #endif