1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
11 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
14 #define CONFIG_SYS_MONITOR_LEN 0xc0000
17 #ifdef CONFIG_NAND_BOOT
18 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
19 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
20 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
22 #define CONFIG_SYS_MONITOR_LEN 0x80000
25 #define SPD_EEPROM_ADDRESS 0x51
27 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
28 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
37 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
38 #define CONFIG_SYS_FLASH_BASE 0x60000000
39 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
41 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
42 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
46 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
47 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
52 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
54 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
56 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
57 FTIM0_NOR_TEADC(0x5) | \
59 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
60 FTIM1_NOR_TRAD_NOR(0x1a) | \
61 FTIM1_NOR_TSEQRAD_NOR(0x13))
62 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
63 FTIM2_NOR_TCH(0x4) | \
64 FTIM2_NOR_TWPH(0xe) | \
66 #define CONFIG_SYS_NOR_FTIM3 0
68 #define CONFIG_SYS_FLASH_QUIET_TEST
69 #define CONFIG_FLASH_SHOW_PROGRESS 45
70 #define CONFIG_SYS_WRITE_SWAPPED_DATA
72 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
73 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
74 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
76 #define CONFIG_SYS_FLASH_EMPTY_INFO
77 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
78 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
81 * NAND Flash Definitions
84 #define CONFIG_SYS_NAND_BASE 0x7e800000
85 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
87 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
89 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
93 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
94 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
95 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
96 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
97 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
98 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
99 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
100 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
102 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
103 FTIM0_NAND_TWP(0x18) | \
104 FTIM0_NAND_TWCHT(0x7) | \
106 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
107 FTIM1_NAND_TWBE(0x39) | \
108 FTIM1_NAND_TRR(0xe) | \
109 FTIM1_NAND_TRP(0x18))
110 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
111 FTIM2_NAND_TREH(0xa) | \
112 FTIM2_NAND_TWHRE(0x1e))
113 #define CONFIG_SYS_NAND_FTIM3 0x0
115 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
116 #define CONFIG_SYS_MAX_NAND_DEVICE 1
123 #ifdef CONFIG_FSL_QIXIS
124 #define QIXIS_BASE 0x7fb00000
125 #define QIXIS_BASE_PHYS QIXIS_BASE
126 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
127 #define QIXIS_LBMAP_SWITCH 6
128 #define QIXIS_LBMAP_MASK 0x0f
129 #define QIXIS_LBMAP_SHIFT 0
130 #define QIXIS_LBMAP_DFLTBANK 0x00
131 #define QIXIS_LBMAP_ALTBANK 0x04
132 #define QIXIS_PWR_CTL 0x21
133 #define QIXIS_PWR_CTL_POWEROFF 0x80
134 #define QIXIS_RST_CTL_RESET 0x44
135 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
136 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
137 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
138 #define QIXIS_CTL_SYS 0x5
139 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
140 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
141 #define QIXIS_RST_FORCE_3 0x45
142 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
143 #define QIXIS_PWR_CTL2 0x21
144 #define QIXIS_PWR_CTL2_PCTL 0x2
146 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
147 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
151 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
152 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
153 CSOR_NOR_NOR_MODE_AVD_NOR | \
157 * QIXIS Timing parameters for IFC GPCM
159 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
160 FTIM0_GPCM_TEADC(0xe) | \
161 FTIM0_GPCM_TEAHC(0xe))
162 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
163 FTIM1_GPCM_TRAD(0x1f))
164 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
165 FTIM2_GPCM_TCH(0xe) | \
166 FTIM2_GPCM_TWP(0xf0))
167 #define CONFIG_SYS_FPGA_FTIM3 0x0
170 #if defined(CONFIG_NAND_BOOT)
171 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
172 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
173 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
174 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
175 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
176 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
177 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
178 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
179 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
180 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
181 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
182 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
183 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
184 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
185 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
186 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
187 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
188 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
189 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
190 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
191 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
192 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
193 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
194 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
195 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
196 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
197 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
198 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
199 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
200 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
201 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
202 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
204 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
205 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
206 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
207 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
208 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
209 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
210 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
211 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
212 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
213 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
214 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
215 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
216 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
217 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
218 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
219 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
220 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
221 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
222 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
223 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
224 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
225 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
226 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
227 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
228 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
229 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
230 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
231 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
232 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
233 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
234 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
235 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
241 #ifndef CONFIG_LPUART
242 #define CONFIG_SYS_NS16550_SERIAL
243 #ifndef CONFIG_DM_SERIAL
244 #define CONFIG_SYS_NS16550_REG_SIZE 1
246 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
256 #define CONFIG_SYS_I2C_EEPROM_NXID
257 #define CONFIG_SYS_EEPROM_BUS_NUM 0
260 * I2C bus multiplexer
262 #define I2C_MUX_PCA_ADDR_PRI 0x77
263 #define I2C_MUX_CH_DEFAULT 0x8
264 #define I2C_MUX_CH_CH7301 0xC
274 #ifdef CONFIG_TSEC_ENET
275 #define CONFIG_MII_DEFAULT_TSEC 3
276 #define CONFIG_TSEC1 1
277 #define CONFIG_TSEC1_NAME "eTSEC1"
278 #define CONFIG_TSEC2 1
279 #define CONFIG_TSEC2_NAME "eTSEC2"
280 #define CONFIG_TSEC3 1
281 #define CONFIG_TSEC3_NAME "eTSEC3"
283 #define TSEC1_PHY_ADDR 1
284 #define TSEC2_PHY_ADDR 2
285 #define TSEC3_PHY_ADDR 3
287 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
288 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
289 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
291 #define TSEC1_PHYIDX 0
292 #define TSEC2_PHYIDX 0
293 #define TSEC3_PHYIDX 0
295 #define CONFIG_FSL_SGMII_RISER 1
296 #define SGMII_RISER_PHY_OFFSET 0x1b
298 #ifdef CONFIG_FSL_SGMII_RISER
299 #define CONFIG_SYS_TBIPA_VALUE 8
304 #define CONFIG_PEN_ADDR_BIG_ENDIAN
305 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
307 #define CONFIG_HWCONFIG
308 #define HWCONFIG_BUFFER_SIZE 256
310 #define CONFIG_FSL_DEVICE_DISABLE
313 #define CONFIG_EXTRA_ENV_SETTINGS \
314 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
315 "initrd_high=0xffffffff\0" \
316 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
318 #define CONFIG_EXTRA_ENV_SETTINGS \
319 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
320 "initrd_high=0xffffffff\0" \
321 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
325 * Miscellaneous configurable options
327 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
329 #define CONFIG_LS102XA_STREAM_ID
335 #include <asm/fsl_secure_boot.h>
336 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */