include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16
  17 #ifdef CONFIG_SD_BOOT
  18 #define CONFIG_SPL_MAX_SIZE             0x1a000
  19 #define CONFIG_SPL_STACK                0x1001d000
  20 #define CONFIG_SPL_PAD_TO               0x1c000
  21
  22 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  23                 CONFIG_SYS_MONITOR_LEN)
  24 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  25 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  26 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  27 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  28 #endif
  29
  30 #ifdef CONFIG_NAND_BOOT
  31 #define CONFIG_SPL_MAX_SIZE             0x1a000
  32 #define CONFIG_SPL_STACK                0x1001d000
  33 #define CONFIG_SPL_PAD_TO               0x1c000
  34
  35 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  36 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  37 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  38
  39 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  40 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  41 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  42 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  43 #define CONFIG_SYS_MONITOR_LEN          0x80000
  44 #endif
  45
  46 #define SPD_EEPROM_ADDRESS              0x51
  47 #define CONFIG_SYS_SPD_BUS_NUM          0
  48
  49 #ifndef CONFIG_SYS_FSL_DDR4
  50 #define CONFIG_SYS_DDR_RAW_TIMING
  51 #endif
  52 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  53
  54 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  55 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  56
  57 #ifdef CONFIG_DDR_ECC
  58 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  59 #endif
  60
  61 /*
  62  * IFC Definitions
  63  */
  64 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  65 #define CONFIG_SYS_FLASH_BASE           0x60000000
  66 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  67
  68 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  69 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  70                                 CSPR_PORT_SIZE_16 | \
  71                                 CSPR_MSEL_NOR | \
  72                                 CSPR_V)
  73 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  74 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  75                                 + 0x8000000) | \
  76                                 CSPR_PORT_SIZE_16 | \
  77                                 CSPR_MSEL_NOR | \
  78                                 CSPR_V)
  79 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  80
  81 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  82                                         CSOR_NOR_TRHZ_80)
  83 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  84                                         FTIM0_NOR_TEADC(0x5) | \
  85                                         FTIM0_NOR_TEAHC(0x5))
  86 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  87                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  88                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  89 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  90                                         FTIM2_NOR_TCH(0x4) | \
  91                                         FTIM2_NOR_TWPH(0xe) | \
  92                                         FTIM2_NOR_TWP(0x1c))
  93 #define CONFIG_SYS_NOR_FTIM3            0
  94
  95 #define CONFIG_SYS_FLASH_QUIET_TEST
  96 #define CONFIG_FLASH_SHOW_PROGRESS      45
  97 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  98
  99 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 100 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 101 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 102
 103 #define CONFIG_SYS_FLASH_EMPTY_INFO
 104 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 105                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 106
 107 /*
 108  * NAND Flash Definitions
 109  */
 110
 111 #define CONFIG_SYS_NAND_BASE            0x7e800000
 112 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 113
 114 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 115
 116 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 117                                 | CSPR_PORT_SIZE_8      \
 118                                 | CSPR_MSEL_NAND        \
 119                                 | CSPR_V)
 120 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 121 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 122                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 123                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 124                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 125                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 126                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 127                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 128
 129 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 130                                         FTIM0_NAND_TWP(0x18)   | \
 131                                         FTIM0_NAND_TWCHT(0x7) | \
 132                                         FTIM0_NAND_TWH(0xa))
 133 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 134                                         FTIM1_NAND_TWBE(0x39)  | \
 135                                         FTIM1_NAND_TRR(0xe)   | \
 136                                         FTIM1_NAND_TRP(0x18))
 137 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 138                                         FTIM2_NAND_TREH(0xa) | \
 139                                         FTIM2_NAND_TWHRE(0x1e))
 140 #define CONFIG_SYS_NAND_FTIM3           0x0
 141
 142 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 143 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 144 #endif
 145
 146 /*
 147  * QIXIS Definitions
 148  */
 149 #define CONFIG_FSL_QIXIS
 150
 151 #ifdef CONFIG_FSL_QIXIS
 152 #define QIXIS_BASE                      0x7fb00000
 153 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 154 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 155 #define QIXIS_LBMAP_SWITCH              6
 156 #define QIXIS_LBMAP_MASK                0x0f
 157 #define QIXIS_LBMAP_SHIFT               0
 158 #define QIXIS_LBMAP_DFLTBANK            0x00
 159 #define QIXIS_LBMAP_ALTBANK             0x04
 160 #define QIXIS_PWR_CTL                   0x21
 161 #define QIXIS_PWR_CTL_POWEROFF          0x80
 162 #define QIXIS_RST_CTL_RESET             0x44
 163 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 164 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 165 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 166 #define QIXIS_CTL_SYS                   0x5
 167 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 168 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 169 #define QIXIS_RST_FORCE_3               0x45
 170 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 171 #define QIXIS_PWR_CTL2                  0x21
 172 #define QIXIS_PWR_CTL2_PCTL             0x2
 173
 174 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 175 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 176                                         CSPR_PORT_SIZE_8 | \
 177                                         CSPR_MSEL_GPCM | \
 178                                         CSPR_V)
 179 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 180 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 181                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 182                                         CSOR_NOR_TRHZ_80)
 183
 184 /*
 185  * QIXIS Timing parameters for IFC GPCM
 186  */
 187 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 188                                         FTIM0_GPCM_TEADC(0xe) | \
 189                                         FTIM0_GPCM_TEAHC(0xe))
 190 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 191                                         FTIM1_GPCM_TRAD(0x1f))
 192 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 193                                         FTIM2_GPCM_TCH(0xe) | \
 194                                         FTIM2_GPCM_TWP(0xf0))
 195 #define CONFIG_SYS_FPGA_FTIM3           0x0
 196 #endif
 197
 198 #if defined(CONFIG_NAND_BOOT)
 199 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 200 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 201 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 202 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 203 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 204 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 205 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 206 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 207 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 208 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 209 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 210 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 211 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 212 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 213 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 214 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 215 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 216 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 217 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 218 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 219 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 220 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 221 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 222 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 223 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 224 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 225 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 226 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 227 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 228 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 229 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 230 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 231 #else
 232 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 233 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 234 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 235 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 236 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 237 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 238 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 239 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 240 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 241 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 242 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 243 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 244 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 245 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 246 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 247 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 248 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 249 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 250 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 251 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 252 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 253 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 254 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 255 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 256 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 257 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 258 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 259 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 260 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 261 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 262 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 263 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 264 #endif
 265
 266 /*
 267  * Serial Port
 268  */
 269 #ifndef CONFIG_LPUART
 270 #define CONFIG_SYS_NS16550_SERIAL
 271 #ifndef CONFIG_DM_SERIAL
 272 #define CONFIG_SYS_NS16550_REG_SIZE     1
 273 #endif
 274 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 275 #endif
 276
 277 /*
 278  * I2C
 279  */
 280
 281 /* GPIO */
 282
 283 /* EEPROM */
 284 #define CONFIG_SYS_I2C_EEPROM_NXID
 285 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 286
 287 /*
 288  * I2C bus multiplexer
 289  */
 290 #define I2C_MUX_PCA_ADDR_PRI            0x77
 291 #define I2C_MUX_CH_DEFAULT              0x8
 292 #define I2C_MUX_CH_CH7301               0xC
 293
 294 /*
 295  * MMC
 296  */
 297
 298 /*
 299  * eTSEC
 300  */
 301
 302 #ifdef CONFIG_TSEC_ENET
 303 #define CONFIG_MII_DEFAULT_TSEC         3
 304 #define CONFIG_TSEC1                    1
 305 #define CONFIG_TSEC1_NAME               "eTSEC1"
 306 #define CONFIG_TSEC2                    1
 307 #define CONFIG_TSEC2_NAME               "eTSEC2"
 308 #define CONFIG_TSEC3                    1
 309 #define CONFIG_TSEC3_NAME               "eTSEC3"
 310
 311 #define TSEC1_PHY_ADDR                  1
 312 #define TSEC2_PHY_ADDR                  2
 313 #define TSEC3_PHY_ADDR                  3
 314
 315 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 316 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 317 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 318
 319 #define TSEC1_PHYIDX                    0
 320 #define TSEC2_PHYIDX                    0
 321 #define TSEC3_PHYIDX                    0
 322
 323 #define CONFIG_FSL_SGMII_RISER          1
 324 #define SGMII_RISER_PHY_OFFSET          0x1b
 325
 326 #ifdef CONFIG_FSL_SGMII_RISER
 327 #define CONFIG_SYS_TBIPA_VALUE          8
 328 #endif
 329
 330 #endif
 331
 332 /* PCIe */
 333 #define CONFIG_PCIE1            /* PCIE controller 1 */
 334 #define CONFIG_PCIE2            /* PCIE controller 2 */
 335
 336 #ifdef CONFIG_PCI
 337 #define CONFIG_PCI_SCAN_SHOW
 338 #endif
 339
 340 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 341 #define CONFIG_LAYERSCAPE_NS_ACCESS
 342 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 343 #define COUNTER_FREQUENCY               12500000
 344
 345 #define CONFIG_HWCONFIG
 346 #define HWCONFIG_BUFFER_SIZE            256
 347
 348 #define CONFIG_FSL_DEVICE_DISABLE
 349
 350 #ifdef CONFIG_LPUART
 351 #define CONFIG_EXTRA_ENV_SETTINGS       \
 352         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 353         "initrd_high=0xffffffff\0"      \
 354         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 355 #else
 356 #define CONFIG_EXTRA_ENV_SETTINGS       \
 357         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 358         "initrd_high=0xffffffff\0"      \
 359         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 360 #endif
 361
 362 /*
 363  * Miscellaneous configurable options
 364  */
 365 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 366
 367 #define CONFIG_LS102XA_STREAM_ID
 368
 369 #define CONFIG_SYS_INIT_SP_OFFSET \
 370         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 371 #define CONFIG_SYS_INIT_SP_ADDR \
 372         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 373
 374 /*
 375  * Environment
 376  */
 377
 378 #include <asm/fsl_secure_boot.h>
 379 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 380
 381 #endif