include/configs/ls1021aiot.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 /*
  15  * Size of malloc() pool
  16  */
  17 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  18
  19 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  20 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  21
  22 #define CONFIG_SYS_CLK_FREQ             100000000
  23 #define CONFIG_DDR_CLK_FREQ             100000000
  24
  25 /*
  26  * DDR: 800 MHz ( 1600 MT/s data rate )
  27  */
  28
  29 #define DDR_SDRAM_CFG                   0x470c0008
  30 #define DDR_CS0_BNDS                    0x008000bf
  31 #define DDR_CS0_CONFIG                  0x80014302
  32 #define DDR_TIMING_CFG_0                0x50550004
  33 #define DDR_TIMING_CFG_1                0xbcb38c56
  34 #define DDR_TIMING_CFG_2                0x0040d120
  35 #define DDR_TIMING_CFG_3                0x010e1000
  36 #define DDR_TIMING_CFG_4                0x00000001
  37 #define DDR_TIMING_CFG_5                0x03401400
  38 #define DDR_SDRAM_CFG_2                 0x00401010
  39 #define DDR_SDRAM_MODE                  0x00061c60
  40 #define DDR_SDRAM_MODE_2                0x00180000
  41 #define DDR_SDRAM_INTERVAL              0x18600618
  42 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  43 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  44 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  45 #define DDR_DDR_CDR1                    0x80040000
  46 #define DDR_DDR_CDR2                    0x00000001
  47 #define DDR_SDRAM_CLK_CNTL              0x02000000
  48 #define DDR_DDR_ZQ_CNTL                 0x89080600
  49 #define DDR_CS0_CONFIG_2                0
  50 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  51 #define SDRAM_CFG2_D_INIT               0x00000010
  52 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  53 #define SDRAM_CFG2_FRC_SR               0x80000000
  54 #define SDRAM_CFG_BI                    0x00000001
  55
  56 #ifdef CONFIG_RAMBOOT_PBL
  57 #define CONFIG_SYS_FSL_PBL_PBI  \
  58         board/freescale/ls1021aiot/ls102xa_pbi.cfg
  59 #endif
  60
  61 #ifdef CONFIG_SD_BOOT
  62 #define CONFIG_SYS_FSL_PBL_RCW  \
  63         board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
  64 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  65 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  66 #define CONFIG_SPL_ENV_SUPPORT
  67 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  68 #define CONFIG_SPL_I2C_SUPPORT
  69 #define CONFIG_SPL_WATCHDOG_SUPPORT
  70 #define CONFIG_SPL_MMC_SUPPORT
  71 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
  72
  73 #define CONFIG_SPL_MAX_SIZE             0x1a000
  74 #define CONFIG_SPL_STACK                0x1001d000
  75 #define CONFIG_SPL_PAD_TO               0x1c000
  76
  77 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  78                 CONFIG_SYS_MONITOR_LEN)
  79 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  80 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  81 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  82 #define CONFIG_SYS_MONITOR_LEN          0x80000
  83 #endif
  84
  85 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  86 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  87
  88 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  89
  90 /*
  91  * Serial Port
  92  */
  93 #define CONFIG_SYS_NS16550_SERIAL
  94 #define CONFIG_SYS_NS16550_REG_SIZE     1
  95 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  96
  97 /*
  98  * I2C
  99  */
 100
 101 #ifndef CONFIG_DM_I2C
 102 #define CONFIG_SYS_I2C
 103 #else
 104 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 105 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
 106 #endif
 107 #define CONFIG_SYS_I2C_MXC
 108 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 109 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 110 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 111
 112 /* EEPROM */
 113 #define CONFIG_ID_EEPROM
 114 #define CONFIG_SYS_I2C_EEPROM_NXID
 115 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 116 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x51
 117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 118
 119 /*
 120  * MMC
 121  */
 122
 123 /* SATA */
 124 #define CONFIG_SCSI_AHCI_PLAT
 125 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
 126 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
 127 #endif
 128 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
 129         PCI_DEVICE_ID_FREESCALE_AHCI}
 130
 131 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
 132 #define CONFIG_SYS_SCSI_MAX_LUN         1
 133 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 134                 CONFIG_SYS_SCSI_MAX_LUN)
 135
 136 /* SPI */
 137 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 138 #define CONFIG_SPI_FLASH_SPANSION
 139 #endif
 140
 141 /* DM SPI */
 142 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 143 #define CONFIG_DM_SPI_FLASH
 144 #endif
 145
 146 /*
 147  * eTSEC
 148  */
 149
 150 #ifdef CONFIG_TSEC_ENET
 151 #define CONFIG_MII_DEFAULT_TSEC         1
 152 #define CONFIG_TSEC1                    1
 153 #define CONFIG_TSEC1_NAME               "eTSEC1"
 154 #define CONFIG_TSEC2                    1
 155 #define CONFIG_TSEC2_NAME               "eTSEC2"
 156
 157 #define TSEC1_PHY_ADDR                  1
 158 #define TSEC2_PHY_ADDR                  3
 159
 160 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 161 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 162
 163 #define TSEC1_PHYIDX                    0
 164 #define TSEC2_PHYIDX                    0
 165
 166 #define CONFIG_ETHPRIME                 "eTSEC2"
 167
 168 #define CONFIG_HAS_ETH0
 169 #define CONFIG_HAS_ETH1
 170 #define CONFIG_HAS_ETH2
 171 #endif
 172
 173 /* PCIe */
 174 #define CONFIG_PCIE1            /* PCIE controler 1 */
 175 #define CONFIG_PCIE2            /* PCIE controler 2 */
 176
 177 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 178
 179 #ifdef CONFIG_PCI
 180 #define CONFIG_PCI_SCAN_SHOW
 181 #endif
 182
 183 #define CONFIG_CMDLINE_TAG
 184
 185 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 186 #define CONFIG_LAYERSCAPE_NS_ACCESS
 187 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 188 #define COUNTER_FREQUENCY               12500000
 189
 190 #define CONFIG_HWCONFIG
 191 #define HWCONFIG_BUFFER_SIZE            256
 192
 193 #define CONFIG_FSL_DEVICE_DISABLE
 194
 195 #define CONFIG_EXTRA_ENV_SETTINGS       \
 196         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 197 "initrd_high=0xffffffff\0"
 198
 199 /*
 200  * Miscellaneous configurable options
 201  */
 202 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 203
 204 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 205
 206 #define CONFIG_LS102XA_STREAM_ID
 207
 208 #define CONFIG_SYS_INIT_SP_OFFSET \
 209         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 210 #define CONFIG_SYS_INIT_SP_ADDR \
 211         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 212
 213 #ifdef CONFIG_SPL_BUILD
 214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 215 #else
 216 /* start of monitor */
 217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 218 #endif
 219
 220 #define CONFIG_SYS_QE_FW_ADDR   0x67f40000
 221
 222 /*
 223  * Environment
 224  */
 225
 226 #define CONFIG_ENV_OVERWRITE
 227
 228 #if defined(CONFIG_SD_BOOT)
 229 #define CONFIG_SYS_MMC_ENV_DEV  0
 230 #endif
 231
 232 #define CONFIG_OF_BOARD_SETUP
 233 #define CONFIG_OF_STDOUT_VIA_ALIAS
 234
 235 #include <asm/fsl_secure_boot.h>
 236
 237 #endif