include/configs/ls1021aiot.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 /*
  14  * DDR: 800 MHz ( 1600 MT/s data rate )
  15  */
  16
  17 #define DDR_SDRAM_CFG                   0x470c0008
  18 #define DDR_CS0_BNDS                    0x008000bf
  19 #define DDR_CS0_CONFIG                  0x80014302
  20 #define DDR_TIMING_CFG_0                0x50550004
  21 #define DDR_TIMING_CFG_1                0xbcb38c56
  22 #define DDR_TIMING_CFG_2                0x0040d120
  23 #define DDR_TIMING_CFG_3                0x010e1000
  24 #define DDR_TIMING_CFG_4                0x00000001
  25 #define DDR_TIMING_CFG_5                0x03401400
  26 #define DDR_SDRAM_CFG_2                 0x00401010
  27 #define DDR_SDRAM_MODE                  0x00061c60
  28 #define DDR_SDRAM_MODE_2                0x00180000
  29 #define DDR_SDRAM_INTERVAL              0x18600618
  30 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  31 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  32 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  33 #define DDR_DDR_CDR1                    0x80040000
  34 #define DDR_DDR_CDR2                    0x00000001
  35 #define DDR_SDRAM_CLK_CNTL              0x02000000
  36 #define DDR_DDR_ZQ_CNTL                 0x89080600
  37 #define DDR_CS0_CONFIG_2                0
  38 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  39 #define SDRAM_CFG2_D_INIT               0x00000010
  40 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  41 #define SDRAM_CFG2_FRC_SR               0x80000000
  42 #define SDRAM_CFG_BI                    0x00000001
  43
  44 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  45 #define CFG_SYS_SDRAM_BASE              CONFIG_SYS_DDR_SDRAM_BASE
  46
  47 /*
  48  * Serial Port
  49  */
  50 #define CFG_SYS_NS16550_CLK             get_serial_clock()
  51
  52 /*
  53  * I2C
  54  */
  55
  56 /*
  57  * MMC
  58  */
  59
  60 /* SATA */
  61 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  62 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
  63 #endif
  64 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
  65         PCI_DEVICE_ID_FREESCALE_AHCI}
  66
  67 /* SPI */
  68
  69 /*
  70  * eTSEC
  71  */
  72
  73 #ifdef CONFIG_TSEC_ENET
  74 #define CONFIG_MII_DEFAULT_TSEC         1
  75 #define CONFIG_TSEC1                    1
  76 #define CONFIG_TSEC1_NAME               "eTSEC1"
  77 #define CONFIG_TSEC2                    1
  78 #define CONFIG_TSEC2_NAME               "eTSEC2"
  79
  80 #define TSEC1_PHY_ADDR                  1
  81 #define TSEC2_PHY_ADDR                  3
  82
  83 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
  84 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
  85
  86 #define TSEC1_PHYIDX                    0
  87 #define TSEC2_PHYIDX                    0
  88 #endif
  89
  90 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
  91
  92 #define CONFIG_PEN_ADDR_BIG_ENDIAN
  93 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
  94
  95 #define CONFIG_HWCONFIG
  96 #define HWCONFIG_BUFFER_SIZE            256
  97
  98 #define CONFIG_FSL_DEVICE_DISABLE
  99
 100 #define CONFIG_EXTRA_ENV_SETTINGS       \
 101         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 102 "initrd_high=0xffffffff\0"
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 108
 109 #define CONFIG_LS102XA_STREAM_ID
 110
 111 #include <asm/fsl_secure_boot.h>
 112
 113 #endif