include/configs/ls1012aqds.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1012AQDS_H__
   8 #define __LS1012AQDS_H__
   9
  10 #include "ls1012a_common.h"
  11
  12 /* DDR */
  13 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  14 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  15 #define CONFIG_NR_DRAM_BANKS            2
  16 #define CONFIG_SYS_SDRAM_SIZE           0x40000000
  17 #define CONFIG_CMD_MEMINFO
  18 #define CONFIG_SYS_MEMTEST_START        0x80000000
  19 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
  20
  21 /*
  22  * QIXIS Definitions
  23  */
  24 #define CONFIG_FSL_QIXIS
  25
  26 #ifdef CONFIG_FSL_QIXIS
  27 #define CONFIG_QIXIS_I2C_ACCESS
  28 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  29 #define QIXIS_LBMAP_BRDCFG_REG          0x04
  30 #define QIXIS_LBMAP_SWITCH              6
  31 #define QIXIS_LBMAP_MASK                0x08
  32 #define QIXIS_LBMAP_SHIFT               0
  33 #define QIXIS_LBMAP_DFLTBANK            0x00
  34 #define QIXIS_LBMAP_ALTBANK             0x08
  35 #define QIXIS_RST_CTL_RESET             0x31
  36 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
  37 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
  38 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
  39 #endif
  40
  41 /*
  42  * I2C bus multiplexer
  43  */
  44 #define I2C_MUX_PCA_ADDR_PRI            0x77
  45 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
  46 #define I2C_RETIMER_ADDR                0x18
  47 #define I2C_MUX_CH_DEFAULT              0x8
  48 #define I2C_MUX_CH_CH7301               0xC
  49 #define I2C_MUX_CH5                     0xD
  50 #define I2C_MUX_CH7                     0xF
  51
  52 #define I2C_MUX_CH_VOL_MONITOR 0xa
  53
  54 /*
  55 * RTC configuration
  56 */
  57 #define RTC
  58 #define CONFIG_RTC_PCF8563 1
  59 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
  60
  61 /* EEPROM */
  62 #define CONFIG_ID_EEPROM
  63 #define CONFIG_SYS_I2C_EEPROM_NXID
  64 #define CONFIG_SYS_EEPROM_BUS_NUM    0
  65 #define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
  66 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
  67 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  68 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  69
  70
  71 /* Voltage monitor on channel 2*/
  72 #define I2C_VOL_MONITOR_ADDR           0x40
  73 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
  74 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
  75 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
  76
  77 /* DSPI */
  78 #define CONFIG_FSL_DSPI1
  79 #define CONFIG_DEFAULT_SPI_BUS 1
  80
  81 #define CONFIG_CMD_SPI
  82 #define MMAP_DSPI          DSPI1_BASE_ADDR
  83
  84 #define CONFIG_SYS_DSPI_CTAR0   1
  85
  86 #define CONFIG_SYS_DSPI_CTAR1   (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  87                                 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  88                                 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
  89                                 DSPI_CTAR_DT(0))
  90 #define CONFIG_SPI_FLASH_SST /* cs1 */
  91
  92 #define CONFIG_SYS_DSPI_CTAR2   (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  93                                 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
  94                                 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
  95                                 DSPI_CTAR_DT(0))
  96 #define CONFIG_SPI_FLASH_STMICRO /* cs2 */
  97
  98 #define CONFIG_SYS_DSPI_CTAR3   (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
  99                                 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
 100                                 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
 101                                 DSPI_CTAR_DT(0))
 102 #define CONFIG_SPI_FLASH_EON /* cs3 */
 103
 104 #define CONFIG_SF_DEFAULT_SPEED      10000000
 105 #define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
 106 #define CONFIG_SF_DEFAULT_BUS        1
 107 #define CONFIG_SF_DEFAULT_CS         0
 108
 109 /*  MMC  */
 110 #ifdef CONFIG_MMC
 111 #define CONFIG_FSL_ESDHC
 112 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 113 #endif
 114
 115 #define CONFIG_PCIE1            /* PCIE controller 1 */
 116
 117 #define CONFIG_PCI_SCAN_SHOW
 118
 119 #define CONFIG_CMD_MEMINFO
 120 #define CONFIG_SYS_MEMTEST_START        0x80000000
 121 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 122
 123 #define CONFIG_MISC_INIT_R
 124
 125 #endif /* __LS1012AQDS_H__ */