include/configs/kmtegr1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME   "kmtegr1"
  24 #define CONFIG_KM_BOARD_NAME   "kmtegr1"
  25 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  26 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  27
  28 #define CONFIG_ENV_ADDR         0xF0100000
  29 #define CONFIG_ENV_OFFSET       0x100000
  30
  31 #define CONFIG_NAND_ECC_BCH
  32 #define CONFIG_NAND_KMETER1
  33 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  34 #define NAND_MAX_CHIPS                          1
  35
  36 /*
  37  * High Level Configuration Options
  38  */
  39 #define CONFIG_E300             1       /* E300 family */
  40 #define CONFIG_QE               1       /* Has QE */
  41
  42 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
  43
  44 /* include common defines/options for all Keymile boards */
  45 #include "km/keymile-common.h"
  46 #include "km/km-powerpc.h"
  47
  48 /*
  49  * System Clock Setup
  50  */
  51 #define CONFIG_83XX_CLKIN               66000000
  52 #define CONFIG_SYS_CLK_FREQ             66000000
  53 #define CONFIG_83XX_PCICLK              66000000
  54
  55 /*
  56  * Bus Arbitration Configuration Register (ACR)
  57  */
  58 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  59 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  60 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  61 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  62
  63 /*
  64  * DDR Setup
  65  */
  66 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  69
  70 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  71 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  72                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  73
  74 #define CFG_83XX_DDR_USES_CS0
  75
  76 /*
  77  * Manually set up DDR parameters
  78  */
  79 #define CONFIG_DDR_II
  80 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  81
  82 /*
  83  * The reserved memory
  84  */
  85 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  86 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  87
  88 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  89 #define CONFIG_SYS_RAMBOOT
  90 #endif
  91
  92 /* Reserve 768 kB for Mon */
  93 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  94
  95 /*
  96  * Initial RAM Base Address Setup
  97  */
  98 #define CONFIG_SYS_INIT_RAM_LOCK
  99 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 100 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
 101 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 102                                                 GENERATED_GBL_DATA_SIZE)
 103
 104 /*
 105  * Init Local Bus Memory Controller:
 106  *
 107  * Bank Bus     Machine PortSz  Size  Device
 108  * ---- ---     ------- ------  -----  ------
 109  *  0   Local   GPCM    16 bit  256MB FLASH
 110  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 111  *
 112  */
 113 /*
 114  * FLASH on the Local Bus
 115  */
 116 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 117
 118
 119 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 120 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 121 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 122
 123 /*
 124  * PRIO1/PIGGY on the local bus CS1
 125  */
 126
 127
 128 /*
 129  * Serial Port
 130  */
 131 #define CONFIG_SYS_NS16550_SERIAL
 132 #define CONFIG_SYS_NS16550_REG_SIZE     1
 133 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 134
 135 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 136 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 137
 138 /*
 139  * QE UEC ethernet configuration
 140  */
 141 #define CONFIG_UEC_ETH
 142 #define CONFIG_ETHPRIME         "UEC0"
 143
 144 #ifdef CONFIG_UEC_ETH1
 145 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 146 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 147 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 148 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 149 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 150 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 151 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 152 #endif
 153
 154 /*
 155  * Environment
 156  */
 157
 158 #ifndef CONFIG_SYS_RAMBOOT
 159 #ifndef CONFIG_ENV_ADDR
 160 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 161                                         CONFIG_SYS_MONITOR_LEN)
 162 #endif
 163 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 164 #ifndef CONFIG_ENV_OFFSET
 165 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 166 #endif
 167
 168 /* Address and size of Redundant Environment Sector     */
 169 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 170                                                 CONFIG_ENV_SECT_SIZE)
 171 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 172
 173 #else /* CFG_SYS_RAMBOOT */
 174 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 175 #define CONFIG_ENV_SIZE         0x2000
 176 #endif /* CFG_SYS_RAMBOOT */
 177
 178 /* I2C */
 179 #define CONFIG_SYS_I2C
 180 #define CONFIG_SYS_NUM_I2C_BUSES        4
 181 #define CONFIG_SYS_I2C_MAX_HOPS         1
 182 #define CONFIG_SYS_I2C_FSL
 183 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 184 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 185 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 186 #define CONFIG_SYS_I2C_OFFSET           0x3000
 187 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 188 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 189 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 190 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 191                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 192                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 193                 {1, {I2C_NULL_HOP} } }
 194
 195 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 196
 197 #if defined(CONFIG_CMD_NAND)
 198 #define CONFIG_NAND_KMETER1
 199 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 200 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 201 #endif
 202
 203 /*
 204  * For booting Linux, the board info and command line data
 205  * have to be in the first 8 MB of memory, since this is
 206  * the maximum mapped by the Linux kernel during initialization.
 207  */
 208 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 209
 210 /*
 211  * Internal Definitions
 212  */
 213 #define BOOTFLASH_START 0xF0000000
 214
 215 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 216
 217 /*
 218  * Environment Configuration
 219  */
 220 #define CONFIG_ENV_OVERWRITE
 221 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 222 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 223 #endif
 224
 225 #ifndef CONFIG_KM_DEF_ARCH
 226 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 227 #endif
 228
 229 #define CONFIG_EXTRA_ENV_SETTINGS \
 230         CONFIG_KM_DEF_ENV                                               \
 231         CONFIG_KM_DEF_ARCH                                              \
 232         "newenv="                                                       \
 233                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 234                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 235         "unlock=yes\0"                                                  \
 236         ""
 237
 238 #if defined(CONFIG_UEC_ETH)
 239 #define CONFIG_HAS_ETH0
 240 #endif
 241
 242 /* QE microcode/firmware address */
 243 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 244 /* between the u-boot partition and env */
 245 #ifndef CONFIG_SYS_QE_FW_ADDR
 246 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
 247 #endif
 248
 249 /*
 250  * System IO Config
 251  */
 252 /* 0x14000180 SICR_1 */
 253 #define CONFIG_SYS_SICRL (0                     \
 254                 | SICR_1_UART1_UART1RTS         \
 255                 | SICR_1_I2C_CKSTOP             \
 256                 | SICR_1_IRQ_A_IRQ              \
 257                 | SICR_1_IRQ_B_IRQ              \
 258                 | SICR_1_GPIO_A_GPIO            \
 259                 | SICR_1_GPIO_B_GPIO            \
 260                 | SICR_1_GPIO_C_GPIO            \
 261                 | SICR_1_GPIO_D_GPIO            \
 262                 | SICR_1_GPIO_E_GPIO            \
 263                 | SICR_1_GPIO_F_GPIO            \
 264                 | SICR_1_USB_A_UART2S           \
 265                 | SICR_1_USB_B_UART2RTS         \
 266                 | SICR_1_FEC1_FEC1              \
 267                 | SICR_1_FEC2_FEC2              \
 268                 )
 269
 270 /* 0x00080400 SICR_2 */
 271 #define CONFIG_SYS_SICRH (0                     \
 272                 | SICR_2_FEC3_FEC3              \
 273                 | SICR_2_HDLC1_A_HDLC1          \
 274                 | SICR_2_ELBC_A_LA              \
 275                 | SICR_2_ELBC_B_LCLK            \
 276                 | SICR_2_HDLC2_A_HDLC2          \
 277                 | SICR_2_USB_D_GPIO             \
 278                 | SICR_2_PCI_PCI                \
 279                 | SICR_2_HDLC1_B_HDLC1          \
 280                 | SICR_2_HDLC1_C_HDLC1          \
 281                 | SICR_2_HDLC2_B_GPIO           \
 282                 | SICR_2_HDLC2_C_HDLC2          \
 283                 | SICR_2_QUIESCE_B              \
 284                 )
 285
 286 /* GPR_1 */
 287 #define CONFIG_SYS_GPR1  0x50008060
 288
 289 #define CONFIG_SYS_GP1DIR 0x00000000
 290 #define CONFIG_SYS_GP1ODR 0x00000000
 291 #define CONFIG_SYS_GP2DIR 0xFF000000
 292 #define CONFIG_SYS_GP2ODR 0x00000000
 293
 294 #define CONFIG_SYS_DDRCDR (\
 295         DDRCDR_EN | \
 296         DDRCDR_PZ_MAXZ | \
 297         DDRCDR_NZ_MAXZ | \
 298         DDRCDR_M_ODR)
 299
 300 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 301 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 302                                          SDRAM_CFG_32_BE | \
 303                                          SDRAM_CFG_SREN | \
 304                                          SDRAM_CFG_HSE)
 305
 306 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 307 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 308 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 309                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 310
 311 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 312                                          CSCONFIG_ODT_RD_NEVER | \
 313                                          CSCONFIG_ODT_WR_ONLY_CURRENT | \
 314                                          CSCONFIG_ROW_BIT_13 | \
 315                                          CSCONFIG_COL_BIT_10)
 316
 317 #define CONFIG_SYS_DDR_MODE     0x47860242
 318 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 319
 320 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 321                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 322                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 323                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 324                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 325                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 326                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 327                                  (0 << TIMING_CFG0_RWT_SHIFT))
 328
 329 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 330                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 331                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 332                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 333                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 334                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 335                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 336                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 337
 338 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 339                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 340                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 341                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 342                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 343                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 344                                  (5 << TIMING_CFG2_CPO_SHIFT))
 345
 346 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 347
 348 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 349 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 350
 351 /* EEprom support */
 352 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 353
 354 /*
 355  * Local Bus Configuration & Clock Setup
 356  */
 357 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 358 #define CONFIG_SYS_LCRR_EADC    0x00010000
 359 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 360
 361 #define CONFIG_SYS_LBC_LBCR     0x00000000
 362
 363 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 364 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 365
 366 #define CONFIG_SYS_APP1_BASE            0xA0000000
 367 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 368 #define CONFIG_SYS_APP2_BASE            0xB0000000
 369 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 370
 371 /* EEprom support */
 372 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 373
 374 /*
 375  * Init Local Bus Memory Controller:
 376  *
 377  * Bank Bus     Machine PortSz  Size  Device
 378  * ---- ---     ------- ------  -----  ------
 379  *  2   Local   UPMA    16 bit  256MB APP1
 380  *  3   Local   GPCM    16 bit  256MB APP2
 381  *
 382  */
 383
 384
 385 /* ethernet port connected to piggy (UEC2) */
 386 #define CONFIG_HAS_ETH1
 387 #define CONFIG_UEC_ETH2
 388 #define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 389 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 390 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 391 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 392 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 393 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 394 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 395
 396 #endif /* __CONFIG_H */