include/configs/kmcent2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2016 Keymile AG
   4  * Rainer Boschung <rainer.boschung@keymile.com>
   5  *
   6  */
   7
   8 #ifndef __KMCENT2_H
   9 #define __KMCENT2_H
  10
  11 /* Application IFC chip selects */
  12 #define SYS_LAWAPP_BASE         0xc0000000
  13 #define SYS_LAWAPP_BASE_PHYS    (0xf00000000ull | SYS_LAWAPP_BASE)
  14
  15 /* Application IFC CS4 MRAM */
  16 #define CFG_SYS_MRAM_BASE               SYS_LAWAPP_BASE
  17 #define SYS_MRAM_BASE_PHYS      SYS_LAWAPP_BASE_PHYS
  18 #define SYS_MRAM_CSPR_EXT       (0x0f)
  19 #define SYS_MRAM_CSPR   (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \
  20                                 CSPR_PORT_SIZE_8 | /* 8 bit */          \
  21                                 CSPR_MSEL_GPCM   | /* msel = gpcm */    \
  22                                 CSPR_V /* bank is valid */)
  23 #define SYS_MRAM_AMASK          IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
  24 #define SYS_MRAM_CSOR           CSOR_GPCM_TRHZ_40
  25 /* MRAM Timing parameters for IFC CS4 */
  26 #define SYS_MRAM_FTIM0  (FTIM0_GPCM_TACSE(0x6) | \
  27                         FTIM0_GPCM_TEADC(0x8)  | \
  28                         FTIM0_GPCM_TEAHC(0x2))
  29 #define SYS_MRAM_FTIM1  (FTIM1_GPCM_TACO(0x2) | \
  30                         FTIM1_GPCM_TRAD(0xe))
  31 #define SYS_MRAM_FTIM2  (FTIM2_GPCM_TCS(0x2) | \
  32                         FTIM2_GPCM_TCH(0x2)  | \
  33                         FTIM2_GPCM_TWP(0x8))
  34 #define SYS_MRAM_FTIM3  0x04000000
  35 #define CFG_SYS_CSPR4_EXT       SYS_MRAM_CSPR_EXT
  36 #define CFG_SYS_CSPR4   SYS_MRAM_CSPR
  37 #define CFG_SYS_AMASK4  SYS_MRAM_AMASK
  38 #define CFG_SYS_CSOR4   SYS_MRAM_CSOR
  39 #define CFG_SYS_CS4_FTIM0       SYS_MRAM_FTIM0
  40 #define CFG_SYS_CS4_FTIM1       SYS_MRAM_FTIM1
  41 #define CFG_SYS_CS4_FTIM2       SYS_MRAM_FTIM2
  42 #define CFG_SYS_CS4_FTIM3       SYS_MRAM_FTIM3
  43
  44 /* Application IFC CS6: BFTIC */
  45 #define SYS_BFTIC_BASE          0xd0000000
  46 #define SYS_BFTIC_BASE_PHYS     (0xf00000000ull | SYS_BFTIC_BASE)
  47 #define SYS_BFTIC_CSPR_EXT      (0x0f)
  48 #define SYS_BFTIC_CSPR  (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
  49                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
  50                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
  51                                 CSPR_V)            /* valid */
  52 #define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
  53 #define SYS_BFTIC_CSOR  CSOR_GPCM_TRHZ_40
  54 /* BFTIC Timing parameters for IFC CS6 */
  55 #define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
  56                                 FTIM0_GPCM_TEADC(0x8) | \
  57                                 FTIM0_GPCM_TEAHC(0x2))
  58 #define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
  59                                 FTIM1_GPCM_TRAD(0x12))
  60 #define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
  61                                 FTIM2_GPCM_TCH(0x1) | \
  62                                 FTIM2_GPCM_TWP(0x12))
  63 #define SYS_BFTIC_FTIM3 0x04000000
  64 #define CFG_SYS_CSPR6_EXT       SYS_BFTIC_CSPR_EXT
  65 #define CFG_SYS_CSPR6   SYS_BFTIC_CSPR
  66 #define CFG_SYS_AMASK6  SYS_BFTIC_AMASK
  67 #define CFG_SYS_CSOR6   SYS_BFTIC_CSOR
  68 #define CFG_SYS_CS6_FTIM0       SYS_BFTIC_FTIM0
  69 #define CFG_SYS_CS6_FTIM1       SYS_BFTIC_FTIM1
  70 #define CFG_SYS_CS6_FTIM2       SYS_BFTIC_FTIM2
  71 #define CFG_SYS_CS6_FTIM3       SYS_BFTIC_FTIM3
  72
  73 /* Application IFC CS7 PAXE */
  74 #define CFG_SYS_PAXE_BASE               0xd8000000
  75 #define SYS_PAXE_BASE_PHYS      (0xf00000000ull | CFG_SYS_PAXE_BASE)
  76 #define SYS_PAXE_CSPR_EXT       (0x0f)
  77 #define SYS_PAXE_CSPR  (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \
  78                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
  79                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
  80                                 CSPR_V)            /* valid */
  81 #define SYS_PAXE_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
  82 #define SYS_PAXE_CSOR  CSOR_GPCM_TRHZ_40
  83 /* PAXE Timing parameters for IFC CS7 */
  84 #define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
  85                         FTIM0_GPCM_TEADC(0x8) | \
  86                         FTIM0_GPCM_TEAHC(0x2))
  87 #define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
  88                         FTIM1_GPCM_TRAD(0x12))
  89 #define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
  90                         FTIM2_GPCM_TCH(0x1) | \
  91                         FTIM2_GPCM_TWP(0x12))
  92 #define SYS_PAXE_FTIM3  0x04000000
  93 #define CFG_SYS_CSPR7_EXT       SYS_PAXE_CSPR_EXT
  94 #define CFG_SYS_CSPR7   SYS_PAXE_CSPR
  95 #define CFG_SYS_AMASK7  SYS_PAXE_AMASK
  96 #define CFG_SYS_CSOR7   SYS_PAXE_CSOR
  97 #define CFG_SYS_CS7_FTIM0       SYS_PAXE_FTIM0
  98 #define CFG_SYS_CS7_FTIM1       SYS_PAXE_FTIM1
  99 #define CFG_SYS_CS7_FTIM2       SYS_PAXE_FTIM2
 100 #define CFG_SYS_CS7_FTIM3       SYS_PAXE_FTIM3
 101
 102 /* PRST */
 103 #define KM_BFTIC4_RST           0
 104 #define KM_DPAXE_RST            1
 105 #define KM_FEMT_RST             3
 106 #define KM_FOAM_RST             4
 107 #define KM_EFE_RST              5
 108 #define KM_ES_PHY_RST           6
 109 #define KM_XES_PHY_RST          7
 110 #define KM_ZL30158_RST          8
 111 #define KM_ZL30364_RST          9
 112 #define KM_BOBCAT_RST           10
 113 #define KM_ETHSW_DDR_RST                12
 114 #define KM_CFE_RST              13
 115 #define KM_PEXSW_RST            14
 116 #define KM_PEXSW_NT_RST         15
 117
 118 /* QRIO GPIOs used for deblocking */
 119 #define KM_I2C_DEBLOCK_PORT     QRIO_GPIO_A
 120 #define KM_I2C_DEBLOCK_SCL      20
 121 #define KM_I2C_DEBLOCK_SDA      21
 122
 123 /* High Level Configuration Options */
 124
 125 #define CFG_RESET_VECTOR_ADDRESS        0xebfffffc
 126
 127 #define CFG_SYS_NUM_CPC         CONFIG_SYS_NUM_DDR_CTLRS
 128
 129 /* Environment in parallel NOR-Flash */
 130 #define CFG_ENV_TOTAL_SIZE              0x040000
 131 #define ENV_DEL_ADDR            0xebf00000      /*direct for newenv*/
 132
 133 /*
 134  * These can be toggled for performance analysis, otherwise use default.
 135  */
 136 #define CFG_SYS_INIT_L2CSR0             L2CSR0_L2E
 137
 138 /* POST memory regions test */
 139 #define CFG_POST CFG_SYS_POST_MEM_REGIONS
 140
 141 /*
 142  *  Config the L3 Cache as L3 SRAM
 143  */
 144 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
 145
 146 #define CFG_SYS_DCSRBAR         0xf0000000
 147 #define CFG_SYS_DCSRBAR_PHYS            0xf00000000ull
 148
 149 /*
 150  * DDR Setup
 151  */
 152 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
 153 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
 154
 155 #define SPD_EEPROM_ADDRESS      0x54
 156 #define CFG_SYS_SDRAM_SIZE      4096    /* for fixed parameter use */
 157
 158 /******************************************************************************
 159  * (PRAM usage)
 160  * ... -------------------------------------------------------
 161  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
 162  * ... |<------------------- pram -------------------------->|
 163  * ... -------------------------------------------------------
 164  * @END_OF_RAM:
 165  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
 166  * @CONFIG_KM_PHRAM: address for /var
 167  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
 168  */
 169
 170 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
 171  * is not valid yet, which is the case for when u-boot copies itself to RAM
 172  */
 173 #define CFG_PRAM                ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
 174
 175 /*
 176  * IFC Definitions
 177  */
 178 /* NOR flash on IFC CS0 */
 179 #define CFG_SYS_FLASH_BASE              0xe8000000
 180 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
 181                                         CFG_SYS_FLASH_BASE)
 182
 183 #define CFG_SYS_NOR_CSPR_EXT    (0x0f)
 184 #define CFG_SYS_NOR_CSPR        (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
 185                                 CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
 186                                 0x00000010 |        /* drive TE high */\
 187                                 CSPR_MSEL_NOR |     /* MSEL = NOR */\
 188                                 CSPR_V)             /* valid */
 189 #define CFG_SYS_NOR_AMASK       IFC_AMASK(64 * 1024 * 1024) /* 64MB */
 190 #define CFG_SYS_NOR_CSOR        (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
 191                                 CSOR_NOR_TRHZ_20 | \
 192                                 CSOR_NOR_BCTLD)
 193
 194 /* NOR Flash Timing Params */
 195 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x1) | \
 196                                 FTIM0_NOR_TEADC(0x7) | \
 197                                 FTIM0_NOR_TEAHC(0x1))
 198 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x1) | \
 199                                 FTIM1_NOR_TRAD_NOR(0x21) | \
 200                                 FTIM1_NOR_TSEQRAD_NOR(0x21))
 201 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCH(0x1) | \
 202                                 FTIM2_NOR_TCS(0x1) | \
 203                                 FTIM2_NOR_TWP(0xb) | \
 204                                 FTIM2_NOR_TWPH(0x6))
 205 #define CFG_SYS_NOR_FTIM3       0x0
 206
 207 #define CFG_SYS_CSPR0_EXT       CFG_SYS_NOR_CSPR_EXT
 208 #define CFG_SYS_CSPR0   CFG_SYS_NOR_CSPR
 209 #define CFG_SYS_AMASK0  CFG_SYS_NOR_AMASK
 210 #define CFG_SYS_CSOR0   CFG_SYS_NOR_CSOR
 211 #define CFG_SYS_CS0_FTIM0       CFG_SYS_NOR_FTIM0
 212 #define CFG_SYS_CS0_FTIM1       CFG_SYS_NOR_FTIM1
 213 #define CFG_SYS_CS0_FTIM2       CFG_SYS_NOR_FTIM2
 214 #define CFG_SYS_CS0_FTIM3       CFG_SYS_NOR_FTIM3
 215
 216 /* More NOR Flash params */
 217
 218 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS}
 219
 220 /* NAND Flash on IFC CS1*/
 221 #define CFG_SYS_NAND_BASE               0xfa000000
 222 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 223
 224 #define CFG_SYS_NAND_CSPR_EXT   (0x0f)
 225 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
 226                                 CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
 227                                 0x00000010 |       /* drive TE high */\
 228                                 CSPR_MSEL_NAND |   /* MSEL = NAND */\
 229                                 CSPR_V)            /* valid */
 230 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024) /* 64kB */
 231
 232 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
 233                                 CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */   \
 234                                 CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */        \
 235                                 CSOR_NAND_RAL_3      | /* RAL = 3Bytes */     \
 236                                 CSOR_NAND_PGS_2K     | /* Page size = 2K */   \
 237                                 CSOR_NAND_SPRZ_128   | /* Spare size = 128 */ \
 238                                 CSOR_NAND_PB(64)     | /* 64 Pages/Block */   \
 239                                 CSOR_NAND_TRHZ_40    | /**/                   \
 240                                 CSOR_NAND_BCTLD)       /**/
 241
 242 /* ONFI NAND Flash mode0 Timing Params */
 243 #define CFG_SYS_NAND_FTIM0      (FTIM0_NAND_TCCST(0x3) | \
 244                                 FTIM0_NAND_TWP(0x8) | \
 245                                 FTIM0_NAND_TWCHT(0x3) | \
 246                                 FTIM0_NAND_TWH(0x5))
 247 #define CFG_SYS_NAND_FTIM1      (FTIM1_NAND_TADLE(0x1e) | \
 248                                 FTIM1_NAND_TWBE(0x1e) | \
 249                                 FTIM1_NAND_TRR(0x6) | \
 250                                 FTIM1_NAND_TRP(0x8))
 251 #define CFG_SYS_NAND_FTIM2      (FTIM2_NAND_TRAD(0x9) | \
 252                                 FTIM2_NAND_TREH(0x5) | \
 253                                 FTIM2_NAND_TWHRE(0x3c))
 254 #define CFG_SYS_NAND_FTIM3      (FTIM3_NAND_TWW(0x1e))
 255
 256 #define CFG_SYS_CSPR1_EXT       CFG_SYS_NAND_CSPR_EXT
 257 #define CFG_SYS_CSPR1   CFG_SYS_NAND_CSPR
 258 #define CFG_SYS_AMASK1  CFG_SYS_NAND_AMASK
 259 #define CFG_SYS_CSOR1   CFG_SYS_NAND_CSOR
 260 #define CFG_SYS_CS1_FTIM0       CFG_SYS_NAND_FTIM0
 261 #define CFG_SYS_CS1_FTIM1       CFG_SYS_NAND_FTIM1
 262 #define CFG_SYS_CS1_FTIM2       CFG_SYS_NAND_FTIM2
 263 #define CFG_SYS_CS1_FTIM3       CFG_SYS_NAND_FTIM3
 264
 265 /* More NAND Flash Params */
 266 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 267
 268 /* QRIO on IFC CS2 */
 269 #define CFG_SYS_QRIO_BASE               0xfb000000
 270 #define CFG_SYS_QRIO_BASE_PHYS  (0xf00000000ull | CFG_SYS_QRIO_BASE)
 271 #define SYS_QRIO_CSPR_EXT       (0x0f)
 272 #define SYS_QRIO_CSPR   (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
 273                                 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
 274                                 0x00000010 |       /* drive TE high */\
 275                                 CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
 276                                 CSPR_V)           /* valid */
 277 #define SYS_QRIO_AMASK  IFC_AMASK(64 * 1024)  /* 64kB */
 278 #define SYS_QRIO_CSOR   (CSOR_GPCM_TRHZ_20 |\
 279                         CSOR_GPCM_BCTLD)
 280 /* QRIO Timing parameters for IFC CS2 */
 281 #define SYS_QRIO_FTIM0  (FTIM0_GPCM_TACSE(0x2) | \
 282                         FTIM0_GPCM_TEADC(0x8) | \
 283                         FTIM0_GPCM_TEAHC(0x2))
 284 #define SYS_QRIO_FTIM1  (FTIM1_GPCM_TACO(0x2) | \
 285                         FTIM1_GPCM_TRAD(0x6))
 286 #define SYS_QRIO_FTIM2  (FTIM2_GPCM_TCS(0x1) | \
 287                         FTIM2_GPCM_TCH(0x1) | \
 288                         FTIM2_GPCM_TWP(0x7))
 289 #define SYS_QRIO_FTIM3  0x04000000
 290 #define CFG_SYS_CSPR2_EXT       SYS_QRIO_CSPR_EXT
 291 #define CFG_SYS_CSPR2   SYS_QRIO_CSPR
 292 #define CFG_SYS_AMASK2  SYS_QRIO_AMASK
 293 #define CFG_SYS_CSOR2   SYS_QRIO_CSOR
 294 #define CFG_SYS_CS2_FTIM0       SYS_QRIO_FTIM0
 295 #define CFG_SYS_CS2_FTIM1       SYS_QRIO_FTIM1
 296 #define CFG_SYS_CS2_FTIM2       SYS_QRIO_FTIM2
 297 #define CFG_SYS_CS2_FTIM3       SYS_QRIO_FTIM3
 298
 299 /* define to use L1 as initial stack */
 300 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000      /* Initial L1 address */
 301 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 302 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
 303 /* The assembler doesn't like typecast */
 304 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
 305         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 306           CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 307 #define CFG_SYS_INIT_RAM_SIZE           0x00004000
 308
 309 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 310
 311 /*
 312  * Serial Port - controlled on board with jumper J8
 313  * open - index 2
 314  * shorted - index 1
 315  * Retain non-DM serial port for debug purposes.
 316  */
 317 #if !CONFIG_IS_ENABLED(DM_SERIAL)
 318 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0) / 2)
 319 #define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR + 0x11C500)
 320 #endif
 321
 322 #ifndef __ASSEMBLY__
 323 void set_sda(int state);
 324 void set_scl(int state);
 325 int get_sda(void);
 326 int get_scl(void);
 327 #endif
 328
 329 /*
 330  * General PCI
 331  * Memory space is mapped 1-1, but I/O space must start from 0.
 332  */
 333 /* controller 1 */
 334 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 335 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 336 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 337 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 338
 339 #define CFG_SYS_BMAN_NUM_PORTALS        10
 340 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 341 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 342 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 343 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 344 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 345 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 346                                         CFG_SYS_BMAN_CENA_SIZE)
 347 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 348 #define CFG_SYS_BMAN_SWP_ISDR_REG       0xE08
 349 #define CFG_SYS_QMAN_NUM_PORTALS        10
 350 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 351 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 352 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 353 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 354 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 355 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 356                                         CFG_SYS_QMAN_CENA_SIZE)
 357 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 358 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 359
 360 /* Qman / Bman */
 361 /* RGMII (FM1@DTESC5) is local managemant interface */
 362 #define CFG_SYS_RGMII2_PHY_ADDR             0x11
 363
 364 /*
 365  * Hardware Watchdog
 366  */
 367 #define CFG_WATCHDOG_PRESC 34   /* wdog prescaler 2^(64-34) ~10min */
 368 #define CFG_WATCHDOG_RC WRC_CHIP        /* reset chip on watchdog event */
 369
 370 /*
 371  * For booting Linux, the board info and command line data
 372  * have to be in the first 64 MB of memory, since this is
 373  * the maximum mapped by the Linux kernel during initialization.
 374  */
 375 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 376
 377 #endif  /* __KMCENT2_H */