1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2016 Keymile AG
4 * Rainer Boschung <rainer.boschung@keymile.com>
11 #define CONFIG_HOSTNAME "kmcent2"
12 #define KM_BOARD_NAME CONFIG_HOSTNAME
15 * The Linux fsl_fman driver needs to be able to process frames with more
16 * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
19 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558"
21 #include "km/keymile-common.h"
23 /* Application IFC chip selects */
24 #define SYS_LAWAPP_BASE 0xc0000000
25 #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
27 /* Application IFC CS4 MRAM */
28 #define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
29 #define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
30 #define SYS_MRAM_CSPR_EXT (0x0f)
31 #define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
32 CSPR_PORT_SIZE_8 | /* 8 bit */ \
33 CSPR_MSEL_GPCM | /* msel = gpcm */ \
34 CSPR_V /* bank is valid */)
35 #define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
36 #define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40
37 /* MRAM Timing parameters for IFC CS4 */
38 #define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
39 FTIM0_GPCM_TEADC(0x8) | \
40 FTIM0_GPCM_TEAHC(0x2))
41 #define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
43 #define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \
44 FTIM2_GPCM_TCH(0x2) | \
46 #define SYS_MRAM_FTIM3 0x04000000
47 #define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
48 #define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
49 #define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
50 #define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
51 #define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
52 #define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
53 #define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
54 #define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
56 /* Application IFC CS6: BFTIC */
57 #define SYS_BFTIC_BASE 0xd0000000
58 #define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE)
59 #define SYS_BFTIC_CSPR_EXT (0x0f)
60 #define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
61 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
62 CSPR_MSEL_GPCM | /* MSEL = GPCM */\
64 #define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */
65 #define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40
66 /* BFTIC Timing parameters for IFC CS6 */
67 #define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
68 FTIM0_GPCM_TEADC(0x8) | \
69 FTIM0_GPCM_TEAHC(0x2))
70 #define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
71 FTIM1_GPCM_TRAD(0x12))
72 #define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
73 FTIM2_GPCM_TCH(0x1) | \
75 #define SYS_BFTIC_FTIM3 0x04000000
76 #define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
77 #define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
78 #define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
79 #define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
80 #define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
81 #define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
82 #define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
83 #define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
85 /* Application IFC CS7 PAXE */
86 #define CONFIG_SYS_PAXE_BASE 0xd8000000
87 #define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
88 #define SYS_PAXE_CSPR_EXT (0x0f)
89 #define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
90 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
91 CSPR_MSEL_GPCM | /* MSEL = GPCM */\
93 #define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */
94 #define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40
95 /* PAXE Timing parameters for IFC CS7 */
96 #define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
97 FTIM0_GPCM_TEADC(0x8) | \
98 FTIM0_GPCM_TEAHC(0x2))
99 #define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
100 FTIM1_GPCM_TRAD(0x12))
101 #define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
102 FTIM2_GPCM_TCH(0x1) | \
103 FTIM2_GPCM_TWP(0x12))
104 #define SYS_PAXE_FTIM3 0x04000000
105 #define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
106 #define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
107 #define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
108 #define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
109 #define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
110 #define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
111 #define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
112 #define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
115 #define KM_BFTIC4_RST 0
116 #define KM_DPAXE_RST 1
117 #define KM_FEMT_RST 3
118 #define KM_FOAM_RST 4
120 #define KM_ES_PHY_RST 6
121 #define KM_XES_PHY_RST 7
122 #define KM_ZL30158_RST 8
123 #define KM_ZL30364_RST 9
124 #define KM_BOBCAT_RST 10
125 #define KM_ETHSW_DDR_RST 12
126 #define KM_CFE_RST 13
127 #define KM_PEXSW_RST 14
128 #define KM_PEXSW_NT_RST 15
130 /* QRIO GPIOs used for deblocking */
131 #define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
132 #define KM_I2C_DEBLOCK_SCL 20
133 #define KM_I2C_DEBLOCK_SDA 21
135 /* High Level Configuration Options */
136 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
138 #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
140 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
142 /* Environment in parallel NOR-Flash */
143 #define CONFIG_ENV_TOTAL_SIZE 0x040000
144 #define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/
147 * These can be toggled for performance analysis, otherwise use default.
149 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
151 /* POST memory regions test */
152 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
155 * Config the L3 Cache as L3 SRAM
157 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
158 #define CONFIG_SYS_L3_SIZE 256 << 10
160 #define CONFIG_SYS_DCSRBAR 0xf0000000
161 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
166 #define CONFIG_VERY_BIG_RAM
167 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
170 #define SPD_EEPROM_ADDRESS 0x54
171 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
173 /******************************************************************************
175 * ... -------------------------------------------------------
176 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
177 * ... |<------------------- pram -------------------------->|
178 * ... -------------------------------------------------------
180 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
181 * @CONFIG_KM_PHRAM: address for /var
182 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
183 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
186 /* size of rootfs in RAM */
187 #define CONFIG_KM_ROOTFSSIZE 0x0
188 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
189 * is not valid yet, which is the case for when u-boot copies itself to RAM
191 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
196 /* NOR flash on IFC CS0 */
197 #define CONFIG_SYS_FLASH_BASE 0xe8000000
198 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
199 CONFIG_SYS_FLASH_BASE)
201 #define CONFIG_SYS_NOR_CSPR_EXT (0x0f)
202 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
203 CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
204 0x00000010 | /* drive TE high */\
205 CSPR_MSEL_NOR | /* MSEL = NOR */\
207 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */
208 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
212 /* NOR Flash Timing Params */
213 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
214 FTIM0_NOR_TEADC(0x7) | \
215 FTIM0_NOR_TEAHC(0x1))
216 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
217 FTIM1_NOR_TRAD_NOR(0x21) | \
218 FTIM1_NOR_TSEQRAD_NOR(0x21))
219 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \
220 FTIM2_NOR_TCS(0x1) | \
221 FTIM2_NOR_TWP(0xb) | \
223 #define CONFIG_SYS_NOR_FTIM3 0x0
225 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
226 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
227 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
228 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
229 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
230 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
231 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
232 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
234 /* More NOR Flash params */
235 #define CONFIG_SYS_FLASH_QUIET_TEST
237 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
239 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
241 /* NAND Flash on IFC CS1*/
242 #define CONFIG_SYS_NAND_BASE 0xfa000000
243 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
245 #define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
246 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
247 CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
248 0x00000010 | /* drive TE high */\
249 CSPR_MSEL_NAND | /* MSEL = NAND */\
251 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
253 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
254 CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \
255 CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \
256 CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \
257 CSOR_NAND_PGS_2K | /* Page size = 2K */ \
258 CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \
259 CSOR_NAND_PB(64) | /* 64 Pages/Block */ \
260 CSOR_NAND_TRHZ_40 | /**/ \
261 CSOR_NAND_BCTLD) /**/
263 /* ONFI NAND Flash mode0 Timing Params */
264 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
265 FTIM0_NAND_TWP(0x8) | \
266 FTIM0_NAND_TWCHT(0x3) | \
268 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
269 FTIM1_NAND_TWBE(0x1e) | \
270 FTIM1_NAND_TRR(0x6) | \
272 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
273 FTIM2_NAND_TREH(0x5) | \
274 FTIM2_NAND_TWHRE(0x3c))
275 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
277 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
278 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
279 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
280 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
281 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
282 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
283 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
284 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
286 /* More NAND Flash Params */
287 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
288 #define CONFIG_SYS_MAX_NAND_DEVICE 1
290 /* QRIO on IFC CS2 */
291 #define CONFIG_SYS_QRIO_BASE 0xfb000000
292 #define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
293 #define SYS_QRIO_CSPR_EXT (0x0f)
294 #define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
295 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
296 0x00000010 | /* drive TE high */\
297 CSPR_MSEL_GPCM | /* MSEL = GPCM */\
299 #define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */
300 #define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\
302 /* QRIO Timing parameters for IFC CS2 */
303 #define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
304 FTIM0_GPCM_TEADC(0x8) | \
305 FTIM0_GPCM_TEAHC(0x2))
306 #define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
307 FTIM1_GPCM_TRAD(0x6))
308 #define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
309 FTIM2_GPCM_TCH(0x1) | \
311 #define SYS_QRIO_FTIM3 0x04000000
312 #define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
313 #define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
314 #define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
315 #define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
316 #define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
317 #define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
318 #define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
319 #define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
321 #define CONFIG_HWCONFIG
323 /* define to use L1 as initial stack */
324 #define CONFIG_SYS_INIT_RAM_LOCK
325 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
326 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
328 /* The assembler doesn't like typecast */
329 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
330 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
331 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
332 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
334 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
336 #define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */
339 * Serial Port - controlled on board with jumper J8
342 * Retain non-DM serial port for debug purposes.
344 #if !defined(CONFIG_DM_SERIAL)
345 #define CONFIG_SYS_NS16550_SERIAL
346 #define CONFIG_SYS_NS16550_REG_SIZE 1
347 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
348 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
352 void set_sda(int state);
353 void set_scl(int state);
360 * Memory space is mapped 1-1, but I/O space must start from 0.
363 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
364 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
365 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
366 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
368 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
369 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
370 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
371 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
372 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
373 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
374 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
375 CONFIG_SYS_BMAN_CENA_SIZE)
376 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
377 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
378 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
379 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
380 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
381 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
382 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
383 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
384 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
385 CONFIG_SYS_QMAN_CENA_SIZE)
386 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
387 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
389 #define CONFIG_SYS_DPAA_FMAN
390 #define CONFIG_SYS_DPAA_PME
392 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
395 /* RGMII (FM1@DTESC5) is local managemant interface */
396 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
401 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */
402 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
405 * For booting Linux, the board info and command line data
406 * have to be in the first 64 MB of memory, since this is
407 * the maximum mapped by the Linux kernel during initialization.
409 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
412 * Environment Configuration
414 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
415 #define CONFIG_KM_DEF_ENV
418 #define __USB_PHY_TYPE utmi
420 #define CONFIG_KM_DEF_ENV_CPU \
421 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
423 "cramfsload ${fdt_addr_r} " \
424 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
425 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
426 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
427 " +${filesize} && " \
428 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
429 " +${filesize} && " \
430 "cp.b ${load_addr_r} " \
431 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
432 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
434 "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
435 " +${filesize} && " \
436 "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
437 " +${filesize} && " \
438 "cp.b ${load_addr_r} " \
439 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
440 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
441 " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
442 "set_fdthigh=true\0" \
447 #define CONFIG_HW_ENV_SETTINGS \
448 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
449 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
452 #define CONFIG_KM_NEW_ENV \
453 "newenv=protect off " __stringify(ENV_DEL_ADDR) \
454 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
455 "erase " __stringify(ENV_DEL_ADDR) \
456 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
457 "protect on " __stringify(ENV_DEL_ADDR) \
458 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
460 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
461 #ifndef CONFIG_KM_DEF_ARCH
462 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
465 #define CONFIG_EXTRA_ENV_SETTINGS \
469 CONFIG_HW_ENV_SETTINGS \
470 "EEprom_ivm=pca9547:70:9\0" \
473 #endif /* __KMCENT2_H */