1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
16 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
18 * (C) Copyright 2010-2011
19 * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
22 #ifndef __CONFIG_KM8321_COMMON_H
23 #define __CONFIG_KM8321_COMMON_H
26 * High Level Configuration Options
28 #define CONFIG_QE /* Has QE */
29 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
31 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
33 /* include common defines/options for all 83xx Keymile boards */
34 #include "km83xx-common.h"
39 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
42 * Hardware Reset Configuration Word
44 #define CONFIG_SYS_HRCW_LOW (\
45 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
46 HRCWL_DDR_TO_SCB_CLK_2X1 | \
47 HRCWL_CSB_TO_CLKIN_2X1 | \
48 HRCWL_CORE_TO_CSB_2_5X1 | \
49 HRCWL_CE_PLL_VCO_DIV_2 | \
52 #define CONFIG_SYS_HRCW_HIGH (\
54 HRCWH_PCI_ARBITER_DISABLE | \
56 HRCWH_FROM_0X00000100 | \
57 HRCWH_BOOTSEQ_DISABLE | \
58 HRCWH_SW_WATCHDOG_DISABLE | \
59 HRCWH_ROM_LOC_LOCAL_16BIT | \
63 #define CONFIG_SYS_DDRCDR (\
69 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
70 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
75 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
76 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
77 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
78 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
80 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
81 CSCONFIG_ODT_WR_CFG | \
82 CSCONFIG_ROW_BIT_13 | \
85 #define CONFIG_SYS_DDR_MODE 0x47860242
86 #define CONFIG_SYS_DDR_MODE2 0x8080c000
88 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
89 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
90 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
91 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
92 (0 << TIMING_CFG0_WWT_SHIFT) | \
93 (0 << TIMING_CFG0_RRT_SHIFT) | \
94 (0 << TIMING_CFG0_WRT_SHIFT) | \
95 (0 << TIMING_CFG0_RWT_SHIFT))
97 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
98 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
99 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
100 (3 << TIMING_CFG1_WRREC_SHIFT) | \
101 (7 << TIMING_CFG1_REFREC_SHIFT) | \
102 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
103 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
104 (3 << TIMING_CFG1_PRETOACT_SHIFT))
106 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
107 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
108 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
109 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
110 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
111 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
112 (5 << TIMING_CFG2_CPO_SHIFT))
114 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
116 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
117 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
120 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
123 * Local Bus Configuration & Clock Setup
125 #define CONFIG_SYS_LCRR_DBYP 0x80000000
126 #define CONFIG_SYS_LCRR_EADC 0x00010000
127 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002
129 #define CONFIG_SYS_LBC_LBCR 0x00000000
134 #define CONFIG_SYS_IBAT7L (0)
135 #define CONFIG_SYS_IBAT7U (0)
136 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
137 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
139 #endif /* __CONFIG_KM8321_COMMON_H */