include/configs/km/pg-wcom-ls102xa.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 Hitachi Power Grids. All rights reserved.
   4  */
   5
   6 #ifndef __CONFIG_PG_WCOM_LS102XA_H
   7 #define __CONFIG_PG_WCOM_LS102XA_H
   8
   9 #define CONFIG_SYS_FSL_CLK
  10
  11 /* include common defines/options for all Keymile boards */
  12 #include "keymile-common.h"
  13
  14 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  15 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  16
  17 #define CONFIG_PRAM                     ((CONFIG_KM_PNVRAM + \
  18                                           CONFIG_KM_PHRAM + \
  19                                           CONFIG_KM_RESERVED_PRAM) >> 10)
  20
  21 #define CONFIG_SYS_CLK_FREQ             66666666
  22
  23 #define PHYS_SDRAM                      0x80000000
  24 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  25
  26 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  27 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  28
  29 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  30 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  31
  32 #define CONFIG_SYS_SPD_BUS_NUM          0
  33 #define SPD_EEPROM_ADDRESS              0x54
  34
  35 /* POST memory regions test */
  36 #define CONFIG_POST                     (CONFIG_SYS_POST_MEM_REGIONS)
  37 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
  38
  39 /*
  40  * IFC Definitions
  41  */
  42 /* NOR Flash Definitions */
  43 #define CONFIG_FSL_IFC
  44 #define CONFIG_SYS_FLASH_BASE           0x60000000
  45 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  46
  47 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  48 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  49                                 CSPR_PORT_SIZE_16 | \
  50                                 CSPR_TE | \
  51                                 CSPR_MSEL_NOR | \
  52                                 CSPR_V)
  53 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(64 * 1024 * 1024)
  54
  55 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_AVD_TGL_PGM_EN | \
  56                                         CSOR_NOR_ADM_SHIFT(0x4) | \
  57                                         CSOR_NOR_NOR_MODE_ASYNC_NOR | \
  58                                         CSOR_NOR_TRHZ_20 | \
  59                                         CSOR_NOR_BCTLD)
  60 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  61                                         FTIM0_NOR_TEADC(0x7) | \
  62                                         FTIM0_NOR_TAVDS(0x0) | \
  63                                         FTIM0_NOR_TEAHC(0x1))
  64 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1) | \
  65                                         FTIM1_NOR_TRAD_NOR(0x21) | \
  66                                         FTIM1_NOR_TSEQRAD_NOR(0x21))
  67 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  68                                         FTIM2_NOR_TCH(0x1) | \
  69                                         FTIM2_NOR_TWPH(0x6) | \
  70                                         FTIM2_NOR_TWP(0xb))
  71 #define CONFIG_SYS_NOR_FTIM3            0
  72
  73 #define CONFIG_SYS_FLASH_QUIET_TEST
  74 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  75
  76 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  77 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
  78 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  79 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  80
  81 #define CONFIG_SYS_FLASH_EMPTY_INFO
  82 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  83
  84 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  85 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  86
  87 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
  88 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
  89 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
  90 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
  91 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
  92 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
  93 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
  94 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
  95
  96 /* NAND Flash Definitions */
  97 #define CONFIG_NAND_FSL_IFC
  98 #define CONFIG_SYS_NAND_BASE            0x68000000
  99 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 100
 101 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 102 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
 103                                 CSPR_PORT_SIZE_8 | \
 104                                 CSPR_TE | \
 105                                 CSPR_MSEL_NAND | \
 106                                 CSPR_V)
 107 #define CONFIG_SYS_NAND_AMASK           IFC_AMASK(64 * 1024)
 108 #define CONFIG_SYS_NAND_CSOR            (CSOR_NAND_ECC_ENC_EN \
 109                                         | CSOR_NAND_ECC_DEC_EN \
 110                                         | CSOR_NAND_ECC_MODE_4 \
 111                                         | CSOR_NAND_RAL_3 \
 112                                         | CSOR_NAND_PGS_2K \
 113                                         | CSOR_NAND_SPRZ_64 \
 114                                         | CSOR_NAND_PB(64) \
 115                                         | CSOR_NAND_TRHZ_40 \
 116                                         | CSOR_NAND_BCTLD)
 117
 118 #define CONFIG_SYS_NAND_ONFI_DETECTION
 119
 120 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x3) | \
 121                                         FTIM0_NAND_TWP(0x8) | \
 122                                         FTIM0_NAND_TWCHT(0x3) | \
 123                                         FTIM0_NAND_TWH(0x5))
 124 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1e) | \
 125                                         FTIM1_NAND_TWBE(0x1e) | \
 126                                         FTIM1_NAND_TRR(0x6) | \
 127                                         FTIM1_NAND_TRP(0x8))
 128 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x9) | \
 129                                         FTIM2_NAND_TREH(0x5) | \
 130                                         FTIM2_NAND_TWHRE(0x3c))
 131 #define CONFIG_SYS_NAND_FTIM3           (FTIM3_NAND_TWW(0x1e))
 132
 133 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 134 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 135 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 136 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 137 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 138 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 139 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 140 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 141
 142 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 143 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 144
 145 /* QRIO FPGA Definitions */
 146 #define CONFIG_SYS_QRIO_BASE            0x70000000
 147 #define CONFIG_SYS_QRIO_BASE_PHYS       CONFIG_SYS_QRIO_BASE
 148
 149 #define CONFIG_SYS_CSPR2_EXT            (0x00)
 150 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
 151                                         CSPR_PORT_SIZE_8 | \
 152                                         CSPR_TE | \
 153                                         CSPR_MSEL_GPCM | \
 154                                         CSPR_V)
 155 #define CONFIG_SYS_AMASK2               IFC_AMASK(64 * 1024)
 156 #define CONFIG_SYS_CSOR2                (CSOR_GPCM_ADM_SHIFT(0x4) | \
 157                                         CSOR_GPCM_TRHZ_20 | \
 158                                         CSOR_GPCM_BCTLD)
 159 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x2) | \
 160                                         FTIM0_GPCM_TEADC(0x8) | \
 161                                         FTIM0_GPCM_TEAHC(0x2))
 162 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x2) | \
 163                                         FTIM1_GPCM_TRAD(0x6))
 164 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x1) | \
 165                                         FTIM2_GPCM_TCH(0x1) | \
 166                                         FTIM2_GPCM_TWP(0x7))
 167 #define CONFIG_SYS_CS2_FTIM3            0x04000000
 168
 169 /*
 170  * Serial Port
 171  */
 172 #define CONFIG_SYS_NS16550_SERIAL
 173 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 174
 175 /*
 176  * I2C
 177  */
 178 #define CONFIG_SYS_I2C_INIT_BOARD
 179
 180 #define CONFIG_I2C_MULTI_BUS
 181 #define CONFIG_SYS_I2C_MAX_HOPS         1
 182 #define CONFIG_SYS_NUM_I2C_BUSES        3
 183 #define I2C_MUX_PCA_ADDR                0x70
 184 #define I2C_MUX_CH_DEFAULT              0x0
 185 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 186                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 187                                         {1, {I2C_NULL_HOP}                 }, \
 188                                 }
 189
 190 /*
 191  * eTSEC
 192  */
 193 #ifdef CONFIG_TSEC_ENET
 194 #define CONFIG_ETHPRIME                 "ethernet@2d90000"
 195 #endif
 196
 197 #define CONFIG_LAYERSCAPE_NS_ACCESS
 198 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 199 #define COUNTER_FREQUENCY               8333333
 200
 201 #define CONFIG_HWCONFIG
 202 #define HWCONFIG_BUFFER_SIZE            256
 203 #define CONFIG_FSL_DEVICE_DISABLE
 204
 205 /*
 206  * Miscellaneous configurable options
 207  */
 208
 209 #define CONFIG_LS102XA_STREAM_ID
 210
 211 #define CONFIG_SYS_INIT_SP_OFFSET \
 212         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 213 #define CONFIG_SYS_INIT_SP_ADDR \
 214         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 215
 216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 217 #define CONFIG_SYS_MONITOR_LEN          0x100000     /* 1Mbyte */
 218 #define CONFIG_SYS_QE_FW_ADDR           0x60020000
 219
 220 #define CONFIG_SYS_BOOTCOUNT_BE
 221
 222 /*
 223  * Environment
 224  */
 225
 226 #define CONFIG_ENV_TOTAL_SIZE           0x40000
 227 #define ENV_DEL_ADDR            CONFIG_ENV_ADDR_REDUND  /* direct for newenv */
 228
 229 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 230 #define CONFIG_KM_DEF_ENV
 231 #endif
 232
 233 #ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
 234 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 235 #endif
 236
 237 #define CONFIG_KM_DEF_ENV_CPU                                           \
 238         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 239         "cramfsloadfdt="                                                \
 240                 "cramfsload ${fdt_addr_r} "                             \
 241                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 242         "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"                       \
 243         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 244                 " +${filesize} && "                                     \
 245                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE)           \
 246                 " +${filesize} && "                                     \
 247                 "cp.b ${load_addr_r} "                                  \
 248                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
 249                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 250                 " +${filesize}\0"                                       \
 251         "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)    \
 252                 " +${filesize} && "                                     \
 253                 "erase " __stringify(CONFIG_SYS_FLASH_BASE)             \
 254                 " +${filesize} && "                                     \
 255                 "cp.b ${load_addr_r} "                                  \
 256                 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "   \
 257                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 258                 " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0"            \
 259         "set_fdthigh=true\0"                    \
 260         "checkfdt=true\0"                                               \
 261         ""
 262
 263 #define CONFIG_KM_NEW_ENV                                               \
 264         "newenv=protect off " __stringify(ENV_DEL_ADDR)                 \
 265                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 266                 "erase " __stringify(ENV_DEL_ADDR)                      \
 267                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "          \
 268                 "protect on " __stringify(ENV_DEL_ADDR)                 \
 269                 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
 270
 271 #define CONFIG_HW_ENV_SETTINGS                                          \
 272         "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,"     \
 273                         "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,"   \
 274                         "asrc,spdif,lpuart1,ftm1\0"
 275
 276 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 277         CONFIG_KM_NEW_ENV                                               \
 278         CONFIG_KM_DEF_ENV                                               \
 279         CONFIG_HW_ENV_SETTINGS                                          \
 280         "EEprom_ivm=pca9547:70:9\0"                                     \
 281         "ethrotate=no\0"                                                \
 282         ""
 283
 284 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 285 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Increase map for Linux */
 286
 287 #endif