include/configs/km/kmp204x-common.h

   1 /*
   2  * (C) Copyright 2013 Keymile AG
   3  * Valentin Longchamp <valentin.longchamp@keymile.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _CONFIG_KMP204X_H
   9 #define _CONFIG_KMP204X_H
  10
  11 #define CONFIG_SYS_TEXT_BASE    0xfff40000
  12
  13 #define CONFIG_KM_DEF_NETDEV    "netdev=eth0\0"
  14
  15 /* an additionnal option is required for UBI as subpage access is
  16  * supported in u-boot */
  17 #define CONFIG_KM_UBI_PART_BOOT_OPTS            ",2048"
  18
  19 #define CONFIG_NAND_ECC_BCH
  20
  21 /* common KM defines */
  22 #include "keymile-common.h"
  23
  24 #define CONFIG_SYS_RAMBOOT
  25 #define CONFIG_RAMBOOT_PBL
  26 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  28 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
  29 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
  30
  31 /* High Level Configuration Options */
  32 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  33 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  34 #define CONFIG_MP                       /* support multiple processors */
  35
  36 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  37 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  38 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  39 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  40 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  41 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  42
  43 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  44
  45 /* Environment in SPI Flash */
  46 #define CONFIG_SYS_EXTRA_ENV_RELOC
  47 #define CONFIG_ENV_IS_IN_SPI_FLASH
  48 #define CONFIG_ENV_SPI_BUS              0
  49 #define CONFIG_ENV_SPI_CS               0
  50 #define CONFIG_ENV_SPI_MAX_HZ           20000000
  51 #define CONFIG_ENV_SPI_MODE             0
  52 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB for u-boot */
  53 #define CONFIG_ENV_SIZE                 0x004000        /* 16K env */
  54 #define CONFIG_ENV_SECT_SIZE            0x010000
  55 #define CONFIG_ENV_OFFSET_REDUND        0x110000
  56 #define CONFIG_ENV_TOTAL_SIZE           0x020000
  57
  58 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  59
  60 #ifndef __ASSEMBLY__
  61 unsigned long get_board_sys_clk(unsigned long dummy);
  62 #endif
  63 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  64
  65 /*
  66  * These can be toggled for performance analysis, otherwise use default.
  67  */
  68 #define CONFIG_SYS_CACHE_STASHING
  69 #define CONFIG_BACKSIDE_L2_CACHE
  70 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  71 #define CONFIG_BTB                      /* toggle branch predition */
  72
  73 #define CONFIG_ENABLE_36BIT_PHYS
  74
  75 #define CONFIG_ADDR_MAP
  76 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  77
  78 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
  79
  80 /*
  81  *  Config the L3 Cache as L3 SRAM
  82  */
  83 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  84 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  85                 CONFIG_RAMBOOT_TEXT_BASE)
  86 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  87 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  88
  89 #define CONFIG_SYS_DCSRBAR              0xf0000000
  90 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  91
  92 /*
  93  * DDR Setup
  94  */
  95 #define CONFIG_VERY_BIG_RAM
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  97 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  98
  99 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 100 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 101
 102 #define CONFIG_DDR_SPD
 103 #define CONFIG_FSL_DDR_INTERACTIVE
 104
 105 #define CONFIG_SYS_SPD_BUS_NUM  0
 106 #define SPD_EEPROM_ADDRESS      0x54
 107 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 108
 109 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 110 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 111
 112 /******************************************************************************
 113  * (PRAM usage)
 114  * ... -------------------------------------------------------
 115  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
 116  * ... |<------------------- pram -------------------------->|
 117  * ... -------------------------------------------------------
 118  * @END_OF_RAM:
 119  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
 120  * @CONFIG_KM_PHRAM: address for /var
 121  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
 122  * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
 123  */
 124
 125 /* size of rootfs in RAM */
 126 #define CONFIG_KM_ROOTFSSIZE    0x0
 127 /* pseudo-non volatile RAM [hex] */
 128 #define CONFIG_KM_PNVRAM        0x80000
 129 /* physical RAM MTD size [hex] */
 130 #define CONFIG_KM_PHRAM         0x100000
 131 /* reserved pram area at the end of memory [hex]
 132  * u-boot reserves some memory for the MP boot page */
 133 #define CONFIG_KM_RESERVED_PRAM 0x1000
 134 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
 135  * is not valid yet, which is the case for when u-boot copies itself to RAM */
 136 #define CONFIG_PRAM             ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
 137
 138 #define CONFIG_KM_CRAMFS_ADDR   0x2000000
 139 #define CONFIG_KM_KERNEL_ADDR   0x1000000       /* max kernel size 15.5Mbytes */
 140 #define CONFIG_KM_FDT_ADDR      0x1F80000       /* max dtb    size  0.5Mbytes */
 141
 142 /*
 143  * Local Bus Definitions
 144  */
 145
 146 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
 147 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_8 | LCRR_EADC_2)
 148
 149 /* Nand Flash */
 150 #define CONFIG_NAND_FSL_ELBC
 151 #define CONFIG_SYS_NAND_BASE            0xffa00000
 152 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 153
 154 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 155 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 156 #define CONFIG_CMD_NAND
 157 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 158
 159 #define CONFIG_BCH
 160
 161 /* NAND flash config */
 162 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 163                                | BR_PS_8               /* Port Size = 8 bit */ \
 164                                | BR_MS_FCM             /* MSEL = FCM */ \
 165                                | BR_V)                 /* valid */
 166
 167 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB       /* length 256K */ \
 168                                | OR_FCM_BCTLD   /* LBCTL not ass */     \
 169                                | OR_FCM_SCY_1   /* 1 clk wait cycle */  \
 170                                | OR_FCM_RST     /* 1 clk read setup */  \
 171                                | OR_FCM_PGS     /* Large page size */   \
 172                                | OR_FCM_CST)    /* 0.25 command setup */
 173
 174 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 175 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 176
 177 /* QRIO FPGA */
 178 #define CONFIG_SYS_QRIO_BASE            0xfb000000
 179 #define CONFIG_SYS_QRIO_BASE_PHYS       0xffb000000ull
 180
 181 #define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
 182                                 | BR_PS_8       /* Port Size 8 bits */ \
 183                                 | BR_DECC_OFF   /* no error corr */ \
 184                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 185                                 | BR_V)         /* valid */
 186
 187 #define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB  /* length 64K */ \
 188                                 | OR_GPCM_BCTLD /* no LCTL assert */ \
 189                                 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
 190                                 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
 191                                 | OR_GPCM_TRLX /* relaxed tmgs */ \
 192                                 | OR_GPCM_EAD) /* extra bus clk cycles */
 193
 194 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
 195 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
 196
 197 /* bootcounter in QRIO */
 198 #define CONFIG_BOOTCOUNT_LIMIT
 199 #define CONFIG_SYS_BOOTCOUNT_ADDR       (CONFIG_SYS_QRIO_BASE + 0x20)
 200
 201 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 202 #define CONFIG_MISC_INIT_F
 203 #define CONFIG_MISC_INIT_R
 204 #define CONFIG_LAST_STAGE_INIT
 205
 206 #define CONFIG_HWCONFIG
 207
 208 /* define to use L1 as initial stack */
 209 #define CONFIG_L1_INIT_RAM
 210 #define CONFIG_SYS_INIT_RAM_LOCK
 211 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 212 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 213 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 214 /* The assembler doesn't like typecast */
 215 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 216         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 217           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 218 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 219
 220 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 221                                         GENERATED_GBL_DATA_SIZE)
 222 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 223
 224 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 225 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 226 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 227
 228 /* Serial Port - controlled on board with jumper J8
 229  * open - index 2
 230  * shorted - index 1
 231  */
 232 #define CONFIG_CONS_INDEX       1
 233 #define CONFIG_SYS_NS16550_SERIAL
 234 #define CONFIG_SYS_NS16550_REG_SIZE     1
 235 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 236
 237 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 238 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 239 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 240 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 241
 242 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 243
 244 /* I2C */
 245
 246 #define CONFIG_SYS_I2C
 247 #define CONFIG_SYS_I2C_INIT_BOARD
 248 #define CONFIG_SYS_I2C_SPEED            100000 /* deblocking */
 249 #define CONFIG_SYS_NUM_I2C_BUSES        3
 250 #define CONFIG_SYS_I2C_MAX_HOPS         1
 251 #define CONFIG_SYS_I2C_FSL              /* Use FSL I2C driver */
 252 #define CONFIG_I2C_MULTI_BUS
 253 #define CONFIG_I2C_CMD_TREE
 254 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 255 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 256 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 257 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 258                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 259                                         {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
 260                                 }
 261 #ifndef __ASSEMBLY__
 262 void set_sda(int state);
 263 void set_scl(int state);
 264 int get_sda(void);
 265 int get_scl(void);
 266 #endif
 267
 268 #define CONFIG_KM_IVM_BUS               1       /* I2C1 (Mux-Port 1)*/
 269
 270 /*
 271  * eSPI - Enhanced SPI
 272  */
 273 #define CONFIG_SPI_FLASH_BAR    /* 4 byte-addressing */
 274 #define CONFIG_SF_DEFAULT_SPEED         20000000
 275 #define CONFIG_SF_DEFAULT_MODE          0
 276
 277 /*
 278  * General PCI
 279  * Memory space is mapped 1-1, but I/O space must start from 0.
 280  */
 281
 282 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 283 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 284 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 285 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 286 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 287 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 288 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 289 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 290 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 291
 292 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 293 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 294 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 295 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 296 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 297 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8010000
 298 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 299 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8010000ull
 300 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 301
 302 /* Qman/Bman */
 303 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 304 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 305 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 306 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 307 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 308 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 309 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 310 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 311 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 312 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 313                                         CONFIG_SYS_BMAN_CENA_SIZE)
 314 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 315 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 316 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 317 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 318 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 319 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 320 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 321 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 322 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 323 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 324 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 325                                         CONFIG_SYS_QMAN_CENA_SIZE)
 326 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 327 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 328
 329 #define CONFIG_SYS_DPAA_FMAN
 330 #define CONFIG_SYS_DPAA_PME
 331 /* Default address of microcode for the Linux Fman driver
 332  * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
 333  * ucode is stored after env, so we got 0x120000.
 334  */
 335 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 336 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
 337 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 338 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 339
 340 #define CONFIG_FMAN_ENET
 341 #define CONFIG_PHYLIB_10G
 342 #define CONFIG_PHY_MARVELL              /* there is a marvell phy */
 343
 344 #define CONFIG_PCI_INDIRECT_BRIDGE
 345
 346 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 347
 348 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
 349 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x11
 350 #define CONFIG_SYS_TBIPA_VALUE  8
 351 #define CONFIG_PHYLIB           /* recommended PHY management */
 352 #define CONFIG_ETHPRIME         "FM1@DTSEC5"
 353 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 354
 355 /*
 356  * Environment
 357  */
 358 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 359 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 360
 361 /*
 362  * Hardware Watchdog
 363  */
 364 #define CONFIG_WATCHDOG                 /* enable CPU watchdog */
 365 #define CONFIG_WATCHDOG_PRESC 34        /* wdog prescaler 2^(64-34) (~10min) */
 366 #define CONFIG_WATCHDOG_RC WRC_CHIP     /* reset chip on watchdog event */
 367
 368
 369 /*
 370  * additionnal command line configuration.
 371  */
 372 #define CONFIG_CMD_PCI
 373 #define CONFIG_CMD_ERRATA
 374
 375 /* we don't need flash support */
 376 #undef CONFIG_FLASH_CFI_MTD
 377 #undef CONFIG_JFFS2_CMDLINE
 378
 379 /*
 380  * For booting Linux, the board info and command line data
 381  * have to be in the first 64 MB of memory, since this is
 382  * the maximum mapped by the Linux kernel during initialization.
 383  */
 384 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 385 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 386
 387 #ifdef CONFIG_CMD_KGDB
 388 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 389 #endif
 390
 391 #define __USB_PHY_TYPE  utmi
 392 #define CONFIG_USB_EHCI_FSL
 393
 394 /*
 395  * Environment Configuration
 396  */
 397 #define CONFIG_ENV_OVERWRITE
 398 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 399 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 400 #endif
 401
 402 #ifndef MTDIDS_DEFAULT
 403 # define MTDIDS_DEFAULT         "nand0=fsl_elbc_nand"
 404 #endif /* MTDIDS_DEFAULT */
 405
 406 #ifndef MTDPARTS_DEFAULT
 407 # define MTDPARTS_DEFAULT       "mtdparts="                     \
 408         "fsl_elbc_nand:"                                                \
 409                 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
 410 #endif /* MTDPARTS_DEFAULT */
 411
 412 /* architecture specific default bootargs */
 413 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 414
 415 /* FIXME: FDT_ADDR is unspecified */
 416 #define CONFIG_KM_DEF_ENV_CPU                                           \
 417         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 418         "cramfsloadfdt="                                                \
 419                 "cramfsload ${fdt_addr_r} "                             \
 420                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 421         "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"              \
 422         "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0"           \
 423         "update="                                                       \
 424                 "sf probe 0;sf erase 0 +${filesize};"                   \
 425                 "sf write ${load_addr_r} 0 ${filesize};\0"              \
 426         "set_fdthigh=true\0"                                            \
 427         "checkfdt=true\0"                                               \
 428         ""
 429
 430 #define CONFIG_HW_ENV_SETTINGS                                          \
 431         "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"                       \
 432         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 433         "usb_dr_mode=host\0"
 434
 435 #define CONFIG_KM_NEW_ENV                                               \
 436         "newenv=sf probe 0;"                                            \
 437                 "sf erase " __stringify(CONFIG_ENV_OFFSET) " "          \
 438                 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
 439
 440 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
 441 #ifndef CONFIG_KM_DEF_ARCH
 442 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 443 #endif
 444
 445 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 446         CONFIG_KM_DEF_ENV                                               \
 447         CONFIG_KM_DEF_ARCH                                              \
 448         CONFIG_KM_NEW_ENV                                               \
 449         CONFIG_HW_ENV_SETTINGS                                          \
 450         "EEprom_ivm=pca9547:70:9\0"                                     \
 451         ""
 452
 453 #endif /* _CONFIG_KMP204X_H */