include/configs/km/km-mpc8360.h

   1 /* KMBEC FPGA (PRIO) */
   2 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
   3 #define CONFIG_SYS_KMBEC_FPGA_SIZE      64
   4
   5 /*
   6  * High Level Configuration Options
   7  */
   8
   9 /*
  10  * QE UEC ethernet configuration
  11  */
  12 #define CONFIG_UEC_ETH1         /* GETH1 */
  13 #define UEC_VERBOSE_DEBUG       1
  14
  15 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
  16 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
  17 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
  18 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
  19 #define CONFIG_SYS_UEC1_PHY_ADDR        0
  20 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
  21 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  22
  23 /*
  24  * System IO Setup
  25  */
  26 #define CONFIG_SYS_SICRH                (SICRH_UC1EOBI | SICRH_UC2E1OBI)
  27
  28 /**
  29  * DDR RAM settings
  30  */
  31 #define CONFIG_SYS_DDR_SDRAM_CFG (\
  32         SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  33         SDRAM_CFG_SREN | \
  34         SDRAM_CFG_HSE)
  35
  36 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  37
  38 #define CONFIG_SYS_DDR_CLK_CNTL (\
  39         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  40
  41 #define CONFIG_SYS_DDR_INTERVAL (\
  42         (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  43         (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
  44
  45 #define CONFIG_SYS_DDR_CS0_BNDS                 0x0000007f
  46
  47 #define CONFIG_SYS_DDRCDR (\
  48         DDRCDR_EN | \
  49         DDRCDR_Q_DRN)
  50 #define CONFIG_SYS_DDR_MODE             0x47860452
  51 #define CONFIG_SYS_DDR_MODE2            0x8080c000
  52
  53 #define CONFIG_SYS_DDR_TIMING_0 (\
  54         (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  55         (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  56         (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  57         (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  58         (0 << TIMING_CFG0_WWT_SHIFT) | \
  59         (0 << TIMING_CFG0_RRT_SHIFT) | \
  60         (0 << TIMING_CFG0_WRT_SHIFT) | \
  61         (0 << TIMING_CFG0_RWT_SHIFT))
  62
  63 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
  64                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  65                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  66                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
  67                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
  68                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  69                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  70                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
  71
  72 #define CONFIG_SYS_DDR_TIMING_2 (\
  73         (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  74         (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  75         (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  76         (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  77         (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  78         (5 << TIMING_CFG2_CPO_SHIFT) | \
  79         (0 << TIMING_CFG2_ADD_LAT_SHIFT))
  80
  81 #define CONFIG_SYS_DDR_TIMING_3                 0x00000000
  82
  83 /* EEprom support */
  84 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
  85
  86 /*
  87  * PAXE on the local bus CS3
  88  */
  89 #define CONFIG_SYS_PAXE_BASE            0xA0000000
  90 #define CONFIG_SYS_PAXE_SIZE            256