6 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
15 * High Level Configuration Options
18 #define CONFIG_MPC5200
19 #define CONFIG_MPX5200 1 /* MPX5200 board */
20 #define CONFIG_MPC5200_DDR 1 /* use DDR RAM */
21 #define CONFIG_IPEK01 /* Motherboard is ipek01 */
23 #define CONFIG_SYS_TEXT_BASE 0xfc000000
25 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
27 #define CONFIG_MISC_INIT_R
29 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
30 #ifdef CONFIG_CMD_KGDB
31 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
35 * Serial console configuration
37 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
38 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
40 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
43 * Video configuration for LIME GDC
46 #define CONFIG_VIDEO_MB862xx
47 #define CONFIG_VIDEO_MB862xx_ACCEL
48 #define VIDEO_FB_16BPP_WORD_SWAP
49 #define CONFIG_VIDEO_LOGO
50 #define CONFIG_VIDEO_BMP_LOGO
51 #define CONFIG_SPLASH_SCREEN
52 #define CONFIG_VIDEO_BMP_GZIP
53 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
54 /* Lime clock frequency */
55 #define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
57 #define CONFIG_SYS_MB862xx_MMR 0x41c767e3
62 * 0x40000000 - 0x4fffffff - PCI Memory
63 * 0x50000000 - 0x50ffffff - PCI IO Space
65 #define CONFIG_PCI_SCAN_SHOW 1
67 #define CONFIG_PCI_MEM_BUS 0x40000000
68 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
69 #define CONFIG_PCI_MEM_SIZE 0x10000000
71 #define CONFIG_PCI_IO_BUS 0x50000000
72 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
73 #define CONFIG_PCI_IO_SIZE 0x01000000
76 #define CONFIG_EEPRO100 1
77 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
80 #define CONFIG_USB_OHCI_NEW
81 #define CONFIG_SYS_OHCI_BE_CONTROLLER
83 #define CONFIG_SYS_USB_OHCI_CPU_INIT
84 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
85 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
86 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
89 * Command line configuration.
91 #define CONFIG_CMD_IRQ /* irqinfo */
92 #define CONFIG_CMD_PCI /* pciinfo */
94 #define CONFIG_SYS_LOWBOOT 1
100 #define CONFIG_PREBOOT "echo;" \
101 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
104 #undef CONFIG_BOOTARGS
106 #define CONFIG_EXTRA_ENV_SETTINGS \
108 "consoledev=ttyPSC0\0" \
109 "hostname=ipek01\0" \
110 "nfsargs=setenv bootargs root=/dev/nfs rw " \
111 "nfsroot=${serverip}:${rootpath}\0" \
112 "ramargs=setenv bootargs root=/dev/ram rw\0" \
113 "addip=setenv bootargs ${bootargs} " \
114 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
115 ":${hostname}:${netdev}:off panic=1\0" \
116 "addtty=setenv bootargs ${bootargs} " \
117 "console=${consoledev},${baudrate}\0" \
118 "flash_nfs=run nfsargs addip addtty;" \
119 "bootm ${kernel_addr} - ${fdtaddr}\0" \
120 "flash_self=run ramargs addip addtty;" \
121 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
122 "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
123 "run nfsargs addip addtty;" \
124 "bootm ${loadaddr} - ${fdtaddr}\0" \
125 "rootpath=/opt/eldk/ppc_6xx\0" \
126 "bootfile=ipek01/uImage\0" \
127 "load=tftp 100000 ipek01/u-boot.bin\0" \
128 "update=protect off FC000000 +60000; era FC000000 +60000; " \
129 "cp.b 100000 FC000000 ${filesize}\0" \
130 "upd=run load;run update\0" \
132 "loadaddr=400000\0" \
133 "fdtfile=ipek01/ipek01.dtb\0" \
136 #define CONFIG_BOOTCOMMAND "run flash_self"
139 * IPB Bus clocking configuration.
141 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
142 /* PCI clock must be 33, because board will not boot */
143 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
146 * Open firmware flat tree support
148 #define OF_CPU "PowerPC,5200@0"
149 #define OF_SOC "soc5200@f0000000"
150 #define OF_TBCLK (bd->bi_busfreq / 4)
152 #define CONFIG_SYS_FLASH_BASE 0xFC000000
153 #define CONFIG_SYS_FLASH_SIZE 0x01000000
154 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
155 CONFIG_SYS_MONITOR_LEN)
157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
158 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
159 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
161 /* use CFI flash driver */
162 #define CONFIG_FLASH_CFI_DRIVER
163 #define CONFIG_SYS_FLASH_CFI
164 #define CONFIG_SYS_FLASH_EMPTY_INFO
165 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
168 * Environment settings
170 #define CONFIG_ENV_IS_IN_FLASH 1
171 #define CONFIG_ENV_SIZE 0x10000
172 #define CONFIG_ENV_SECT_SIZE 0x20000
173 #define CONFIG_ENV_OVERWRITE 1
174 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
175 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
180 #define CONFIG_SYS_MBAR 0xf0000000
181 #define CONFIG_SYS_SDRAM_BASE 0x00000000
182 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
183 #define CONFIG_SYS_SRAM_BASE 0xF1000000
184 #define CONFIG_SYS_SRAM_SIZE 0x00200000
185 #define CONFIG_SYS_LIME_BASE 0xE4000000
186 #define CONFIG_SYS_LIME_SIZE 0x04000000
187 #define CONFIG_SYS_FPGA_BASE 0xC0000000
188 #define CONFIG_SYS_FPGA_SIZE 0x10000000
189 #define CONFIG_SYS_MPEG_BASE 0xe2000000
190 #define CONFIG_SYS_MPEG_SIZE 0x01000000
191 #define CONFIG_SYS_CF_BASE 0xe1000000
192 #define CONFIG_SYS_CF_SIZE 0x01000000
194 /* Use SRAM until RAM will be available */
195 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
196 /* End of used area in DPRAM */
197 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
200 GENERATED_GBL_DATA_SIZE)
201 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
203 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
204 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
205 # define CONFIG_SYS_RAMBOOT 1
208 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
209 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
210 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
213 * Ethernet configuration
215 #define CONFIG_MPC5xxx_FEC 1
216 #define CONFIG_MPC5xxx_FEC_MII100
217 #define CONFIG_PHY_ADDR 0x00
222 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
225 * Miscellaneous configurable options
227 #define CONFIG_SYS_LONGHELP /* undef to save memory */
228 #ifdef CONFIG_CMD_KGDB
229 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
231 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
233 /* Print Buffer Size */
234 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
235 sizeof(CONFIG_SYS_PROMPT) + 16)
236 /* max number of command args */
237 #define CONFIG_SYS_MAXARGS 16
238 /* Boot Argument Buffer Size */
239 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
241 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
242 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
244 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
247 * Various low-level settings
249 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
250 #define CONFIG_SYS_HID0_FINAL HID0_ICE
252 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
253 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
254 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
255 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
256 #define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
257 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
258 #define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
259 #define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
260 #define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
261 #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
262 #define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
263 #define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
264 #define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
265 #define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
267 #ifdef CONFIG_SYS_PCISPEED_66
268 #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
269 #define CONFIG_SYS_CS1_CFG 0x0004FB00
270 #define CONFIG_SYS_CS2_CFG 0x0006F900
272 #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
273 #define CONFIG_SYS_CS1_CFG 0x0001FB00
274 #define CONFIG_SYS_CS2_CFG 0x0002F90C
278 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
279 * waitstates, writeswap and readswap enabled
281 #define CONFIG_SYS_CS3_CFG 0x00FFFB0C
282 #define CONFIG_SYS_CS6_CFG 0x00FFFB0C
283 #define CONFIG_SYS_CS7_CFG 0x4040751C
285 #define CONFIG_SYS_CS_BURST 0x00000000
286 #define CONFIG_SYS_CS_DEADCYCLE 0x33330000
288 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
290 /*-----------------------------------------------------------------------
292 *-----------------------------------------------------------------------
294 #define CONFIG_USB_CLOCK 0x0001BBBB
295 #define CONFIG_USB_CONFIG 0x00005000
297 /*-----------------------------------------------------------------------
298 * IDE/ATA stuff Supports IDE harddisk
299 *-----------------------------------------------------------------------
301 #define CONFIG_IDE_PREINIT
303 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
304 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
306 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
308 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
310 /* Offset for data I/O */
311 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
313 /* Offset for normal register accesses */
314 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
316 /* Offset for alternate registers */
317 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
319 /* Interval between registers */
320 #define CONFIG_SYS_ATA_STRIDE 4
322 #endif /* __CONFIG_H */