3bd938efd927ce15e8b47b5ae478ccf73361d664
[platform/kernel/u-boot.git] / include / configs / ipek01.h
1 /*
2  * (C) Copyright 2006
3  * MicroSys GmbH
4  *
5  * (C) Copyright 2009
6  * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15  * High Level Configuration Options
16  */
17
18 #define CONFIG_MPC5200
19 #define CONFIG_MPX5200          1       /* MPX5200 board */
20 #define CONFIG_MPC5200_DDR      1       /* use DDR RAM */
21 #define CONFIG_IPEK01                   /* Motherboard is ipek01 */
22
23 #define CONFIG_SYS_TEXT_BASE    0xfc000000
24
25 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz */
26
27 #define CONFIG_MISC_INIT_R
28
29 #define CONFIG_SYS_CACHELINE_SIZE       32 /* For MPC5xxx CPUs */
30 #ifdef CONFIG_CMD_KGDB
31 #define CONFIG_SYS_CACHELINE_SHIFT      5  /* log base 2 of the above value */
32 #endif
33
34 /*
35  * Serial console configuration
36  */
37 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
38 #define CONFIG_BAUDRATE         115200  /* ... at 9600 bps */
39 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
40
41 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
42
43 /*
44  * Video configuration for LIME GDC
45  */
46 #ifdef CONFIG_VIDEO
47 #define CONFIG_VIDEO_MB862xx
48 #define CONFIG_VIDEO_MB862xx_ACCEL
49 #define VIDEO_FB_16BPP_WORD_SWAP
50 #define CONFIG_VIDEO_LOGO
51 #define CONFIG_VIDEO_BMP_LOGO
52 #define CONFIG_SPLASH_SCREEN
53 #define CONFIG_VIDEO_BMP_GZIP
54 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
55 /* Lime clock frequency */
56 #define CONFIG_SYS_MB862xx_CCF  0x90000 /* geo 166MHz other 133MHz */
57 /* SDRAM parameter */
58 #define CONFIG_SYS_MB862xx_MMR  0x41c767e3
59 #endif
60
61 /*
62  * PCI Mapping:
63  * 0x40000000 - 0x4fffffff - PCI Memory
64  * 0x50000000 - 0x50ffffff - PCI IO Space
65  */
66 #define CONFIG_PCI_SCAN_SHOW    1
67
68 #define CONFIG_PCI_MEM_BUS      0x40000000
69 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
70 #define CONFIG_PCI_MEM_SIZE     0x10000000
71
72 #define CONFIG_PCI_IO_BUS       0x50000000
73 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
74 #define CONFIG_PCI_IO_SIZE      0x01000000
75
76 #define CONFIG_MII              1
77 #define CONFIG_EEPRO100         1
78 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
79
80 /* Partitions */
81 #define CONFIG_DOS_PARTITION
82
83 /* USB */
84 #define CONFIG_USB_OHCI_NEW
85 #define CONFIG_SYS_OHCI_BE_CONTROLLER
86
87 #define CONFIG_SYS_USB_OHCI_CPU_INIT
88 #define CONFIG_SYS_USB_OHCI_REGS_BASE           MPC5XXX_USB
89 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "mpc5200"
90 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
91
92 /*
93  * Command line configuration.
94  */
95 #ifdef CONFIG_VIDEO
96 #define CONFIG_CMD_BMP          /* BMP support */
97 #endif
98 #define CONFIG_CMD_DATE         /* support for RTC, date/time...*/
99 #define CONFIG_CMD_IDE          /* IDE harddisk support */
100 #define CONFIG_CMD_IRQ          /* irqinfo */
101 #define CONFIG_CMD_PCI          /* pciinfo */
102
103 #define CONFIG_SYS_LOWBOOT      1
104
105 /*
106  * Autobooting
107  */
108
109 #define CONFIG_PREBOOT  "echo;" \
110         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
111         "echo"
112
113 #undef  CONFIG_BOOTARGS
114
115 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
116         "netdev=eth0\0"                                                 \
117         "consoledev=ttyPSC0\0"                                          \
118         "hostname=ipek01\0"                                             \
119         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
120                 "nfsroot=${serverip}:${rootpath}\0"                     \
121         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
122         "addip=setenv bootargs ${bootargs} "                            \
123                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
124                 ":${hostname}:${netdev}:off panic=1\0"                  \
125         "addtty=setenv bootargs ${bootargs} "                           \
126                 "console=${consoledev},${baudrate}\0"                   \
127         "flash_nfs=run nfsargs addip addtty;"                           \
128                 "bootm ${kernel_addr} - ${fdtaddr}\0"                   \
129         "flash_self=run ramargs addip addtty;"                          \
130                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"     \
131         "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};"  \
132                 "run nfsargs addip addtty;"                             \
133                  "bootm ${loadaddr} - ${fdtaddr}\0"                     \
134         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
135         "bootfile=ipek01/uImage\0"                                      \
136         "load=tftp 100000 ipek01/u-boot.bin\0"                          \
137         "update=protect off FC000000 +60000; era FC000000 +60000; "     \
138                 "cp.b 100000 FC000000 ${filesize}\0"                    \
139         "upd=run load;run update\0"                                     \
140         "fdtaddr=800000\0"                                              \
141         "loadaddr=400000\0"                                             \
142         "fdtfile=ipek01/ipek01.dtb\0"                                   \
143         ""
144
145 #define CONFIG_BOOTCOMMAND      "run flash_self"
146
147 /*
148  * IPB Bus clocking configuration.
149  */
150 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* for 133MHz */
151 /* PCI clock must be 33, because board will not boot */
152 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2     /* for 66MHz */
153
154 /*
155  * Open firmware flat tree support
156  */
157 #define OF_CPU                  "PowerPC,5200@0"
158 #define OF_SOC                  "soc5200@f0000000"
159 #define OF_TBCLK                (bd->bi_busfreq / 4)
160
161 /*
162  * I2C configuration
163  */
164 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
165 #define CONFIG_SYS_I2C_MODULE   2       /* Select I2C module #1 or #2 */
166
167 #define CONFIG_SYS_I2C_SPEED    100000  /* 100 kHz */
168 #define CONFIG_SYS_I2C_SLAVE    0x7F
169
170 /*
171  * EEPROM configuration
172  */
173 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
177
178 /*
179  * RTC configuration
180  */
181 #define CONFIG_RTC_PCF8563
182 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
183
184 #define CONFIG_SYS_FLASH_BASE           0xFC000000
185 #define CONFIG_SYS_FLASH_SIZE           0x01000000
186 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + \
187                                          CONFIG_SYS_MONITOR_LEN)
188
189 #define CONFIG_SYS_MAX_FLASH_BANKS      1    /* max num of memory banks */
190 #define CONFIG_SYS_MAX_FLASH_SECT       256  /* max num of sects on one chip */
191 #define CONFIG_SYS_FLASH_PROTECTION  /* "Real" (hardware) sectors protection */
192
193 /* use CFI flash driver */
194 #define CONFIG_FLASH_CFI_DRIVER
195 #define CONFIG_SYS_FLASH_CFI
196 #define CONFIG_SYS_FLASH_EMPTY_INFO
197 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
198
199 /*
200  * Environment settings
201  */
202 #define CONFIG_ENV_IS_IN_FLASH          1
203 #define CONFIG_ENV_SIZE                 0x10000
204 #define CONFIG_ENV_SECT_SIZE            0x20000
205 #define CONFIG_ENV_OVERWRITE            1
206 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
207 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
208
209 /*
210  * Memory map
211  */
212 #define CONFIG_SYS_MBAR                 0xf0000000
213 #define CONFIG_SYS_SDRAM_BASE           0x00000000
214 #define CONFIG_SYS_DEFAULT_MBAR         0x80000000
215 #define CONFIG_SYS_SRAM_BASE            0xF1000000
216 #define CONFIG_SYS_SRAM_SIZE            0x00200000
217 #define CONFIG_SYS_LIME_BASE            0xE4000000
218 #define CONFIG_SYS_LIME_SIZE            0x04000000
219 #define CONFIG_SYS_FPGA_BASE            0xC0000000
220 #define CONFIG_SYS_FPGA_SIZE            0x10000000
221 #define CONFIG_SYS_MPEG_BASE            0xe2000000
222 #define CONFIG_SYS_MPEG_SIZE            0x01000000
223 #define CONFIG_SYS_CF_BASE              0xe1000000
224 #define CONFIG_SYS_CF_SIZE              0x01000000
225
226 /* Use SRAM until RAM will be available */
227 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
228 /* End of used area in DPRAM */
229 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
230
231 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
232                                          GENERATED_GBL_DATA_SIZE)
233 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
234
235 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
236 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
237 #   define CONFIG_SYS_RAMBOOT           1
238 #endif
239
240 #define CONFIG_SYS_MONITOR_LEN  (384 << 10)  /* Reserve 384 kB for Monitor */
241 #define CONFIG_SYS_MALLOC_LEN   (4 << 20)    /* Reserve 128 kB for malloc() */
242 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)    /* Initial Memory map for Linux */
243
244 /*
245  * Ethernet configuration
246  */
247 #define CONFIG_MPC5xxx_FEC              1
248 #define CONFIG_MPC5xxx_FEC_MII100
249 #define CONFIG_PHY_ADDR                 0x00
250
251 /*
252  * GPIO configuration
253  */
254 #define CONFIG_SYS_GPS_PORT_CONFIG      0x1d556624
255
256 /*
257  * Miscellaneous configurable options
258  */
259 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
260 #ifdef CONFIG_CMD_KGDB
261 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
262 #else
263 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
264 #endif
265 /* Print Buffer Size */
266 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
267                                          sizeof(CONFIG_SYS_PROMPT) + 16)
268 /* max number of command args */
269 #define CONFIG_SYS_MAXARGS              16
270 /* Boot Argument Buffer Size */
271 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
272
273 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
274 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1...15 MB in DRAM */
275
276 #define CONFIG_SYS_LOAD_ADDR            0x100000 /* default load address */
277
278 /*
279  * Various low-level settings
280  */
281 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
282 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
283
284 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
285 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
286 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
287 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
288 #define CONFIG_SYS_CS1_START            CONFIG_SYS_SRAM_BASE
289 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_SRAM_SIZE
290 #define CONFIG_SYS_CS3_START            CONFIG_SYS_LIME_BASE
291 #define CONFIG_SYS_CS3_SIZE             CONFIG_SYS_LIME_SIZE
292 #define CONFIG_SYS_CS6_START            CONFIG_SYS_FPGA_BASE
293 #define CONFIG_SYS_CS6_SIZE             CONFIG_SYS_FPGA_SIZE
294 #define CONFIG_SYS_CS5_START            CONFIG_SYS_CF_BASE
295 #define CONFIG_SYS_CS5_SIZE             CONFIG_SYS_CF_SIZE
296 #define CONFIG_SYS_CS7_START            CONFIG_SYS_MPEG_BASE
297 #define CONFIG_SYS_CS7_SIZE             CONFIG_SYS_MPEG_SIZE
298
299 #ifdef CONFIG_SYS_PCISPEED_66
300 #define CONFIG_SYS_BOOTCS_CFG           0x0006F900
301 #define CONFIG_SYS_CS1_CFG              0x0004FB00
302 #define CONFIG_SYS_CS2_CFG              0x0006F900
303 #else
304 #define CONFIG_SYS_BOOTCS_CFG           0x0002F900
305 #define CONFIG_SYS_CS1_CFG              0x0001FB00
306 #define CONFIG_SYS_CS2_CFG              0x0002F90C
307 #endif
308
309 /*
310  * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
311  * waitstates, writeswap and readswap enabled
312  */
313 #define CONFIG_SYS_CS3_CFG              0x00FFFB0C
314 #define CONFIG_SYS_CS6_CFG              0x00FFFB0C
315 #define CONFIG_SYS_CS7_CFG              0x4040751C
316
317 #define CONFIG_SYS_CS_BURST             0x00000000
318 #define CONFIG_SYS_CS_DEADCYCLE         0x33330000
319
320 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
321
322 /*-----------------------------------------------------------------------
323  * USB stuff
324  *-----------------------------------------------------------------------
325  */
326 #define CONFIG_USB_CLOCK                0x0001BBBB
327 #define CONFIG_USB_CONFIG               0x00005000
328
329 /*-----------------------------------------------------------------------
330  * IDE/ATA stuff Supports IDE harddisk
331  *-----------------------------------------------------------------------
332  */
333 #define CONFIG_IDE_PREINIT
334
335 #define CONFIG_SYS_IDE_MAXBUS           1 /* max. 1 IDE bus */
336 #define CONFIG_SYS_IDE_MAXDEVICE        2 /* max. 2 drives per IDE bus */
337
338 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
339
340 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
341
342 /* Offset for data I/O */
343 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
344
345 /* Offset for normal register accesses */
346 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
347
348 /* Offset for alternate registers */
349 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
350
351 /* Interval between registers */
352 #define CONFIG_SYS_ATA_STRIDE           4
353
354 #endif /* __CONFIG_H */