include/configs/io64.h

   1 /*
   2  * (C) Copyright 2011
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * based on kilauea.h
   6  * by Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  * and Grant Erickson <gerickson@nuovations.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 /************************************************************************
  13  * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
  14  ***********************************************************************/
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*-----------------------------------------------------------------------
  20  * High Level Configuration Options
  21  *----------------------------------------------------------------------*/
  22 #define CONFIG_IO64             1               /* Board is Io64 */
  23 #define CONFIG_405EX            1               /* Specifc 405EX support*/
  24 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  25
  26 #ifndef CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  28 #endif
  29
  30 /*
  31  * CHIP_21 errata
  32  */
  33 #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
  34
  35 /*
  36  * Include common defines/options for all AMCC eval boards
  37  */
  38 #define CONFIG_HOSTNAME         io64
  39 #define CONFIG_IDENT_STRING     " io64 0.02"
  40 #include "amcc-common.h"
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F
  43 #define CONFIG_BOARD_EARLY_INIT_R
  44 #define CONFIG_MISC_INIT_R
  45 #define CONFIG_LAST_STAGE_INIT
  46
  47 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* ignore keypress on bootdelay==0 */
  48
  49 /*-----------------------------------------------------------------------
  50  * Base addresses -- Note these are effective addresses where the
  51  * actual resources get mapped (not physical addresses)
  52  *----------------------------------------------------------------------*/
  53 #define CONFIG_SYS_FLASH_BASE           0xFC000000
  54 #define CONFIG_SYS_NVRAM_BASE           0xF0000000
  55 #define CONFIG_SYS_FPGA0_BASE           0xF0100000
  56 #define CONFIG_SYS_FPGA1_BASE           0xF0108000
  57 #define CONFIG_SYS_LATCH_BASE           0xF0200000
  58
  59 /*-----------------------------------------------------------------------
  60  * Initial RAM & Stack Pointer Configuration Options
  61  *
  62  *   There are traditionally three options for the primordial
  63  *   (i.e. initial) stack usage on the 405-series:
  64  *
  65  *      1) On-chip Memory (OCM) (i.e. SRAM)
  66  *      2) Data cache
  67  *      3) SDRAM
  68  *
  69  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  70  *   the latter of which is less than desireable since it requires
  71  *   setting up the SDRAM and ECC in assembly code.
  72  *
  73  *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  74  *   select on the External Bus Controller (EBC) and then select a
  75  *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  76  *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  77  *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  78  *   physical SDRAM to use (3).
  79  *-----------------------------------------------------------------------*/
  80
  81 #define CONFIG_SYS_INIT_DCACHE_CS       4
  82
  83 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
  84 #define CONFIG_SYS_INIT_RAM_ADDR \
  85         (CONFIG_SYS_SDRAM_BASE + (1 << 30))     /*  1 GiB */
  86 #else
  87 #define CONFIG_SYS_INIT_RAM_ADDR \
  88         (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
  89 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  90
  91 #define CONFIG_SYS_INIT_RAM_SIZE \
  92         (4 << 10)                               /*  4 KiB */
  93 #define CONFIG_SYS_GBL_DATA_OFFSET \
  94         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  95
  96 /*
  97  * If the data cache is being used for the primordial stack and global
  98  * data area, the POST word must be placed somewhere else. The General
  99  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
 100  * its compare and mask register contents across reset, so it is used
 101  * for the POST word.
 102  */
 103
 104 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
 105 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 106 # define CONFIG_SYS_POST_WORD_ADDR \
 107         (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 108 #else
 109 # define CONFIG_SYS_INIT_EXTRA_SIZE     16
 110 # define CONFIG_SYS_INIT_SP_OFFSET \
 111         (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
 112 # define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
 113 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 114
 115 /*-----------------------------------------------------------------------
 116  * Serial Port
 117  *----------------------------------------------------------------------*/
 118 #define CONFIG_CONS_INDEX       1       /* Use UART0 */
 119 #define CONFIG_SYS_BASE_BAUD    691200
 120
 121 /*-----------------------------------------------------------------------
 122  * Environment
 123  *----------------------------------------------------------------------*/
 124 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 125
 126 /*-----------------------------------------------------------------------
 127  * FLASH related
 128  *----------------------------------------------------------------------*/
 129 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible */
 130 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver */
 131
 132 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 133 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 134 #define CONFIG_SYS_MAX_FLASH_SECT       512
 135
 136 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000
 137 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 138
 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 140 #define CONFIG_SYS_FLASH_EMPTY_INFO
 141
 142 #ifdef CONFIG_ENV_IS_IN_FLASH
 143 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 144 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 145 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector */
 146
 147 /* Address and size of Redundant Environment Sector */
 148 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 149 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 150 #endif /* CONFIG_ENV_IS_IN_FLASH */
 151
 152 /* Gbit PHYs */
 153 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 154 #define CONFIG_BITBANGMII_MULTI
 155
 156 #define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 12) /* MDIO is GPIO12 */
 157 #define CONFIG_SYS_MDC_PIN   (0x80000000 >> 13) /* MDC  is GPIO13 */
 158
 159 #define CONFIG_SYS_GBIT_MII_BUSNAME     "io_miiphy0"
 160
 161 #define CONFIG_SYS_MDIO1_PIN  (0x80000000 >> 2) /* MDIO is GPIO2 */
 162 #define CONFIG_SYS_MDC1_PIN   (0x80000000 >> 3) /* MDC  is GPIO3 */
 163
 164 #define CONFIG_SYS_GBIT_MII1_BUSNAME    "io_miiphy1"
 165
 166 /*-----------------------------------------------------------------------
 167  * DDR SDRAM
 168  *----------------------------------------------------------------------*/
 169 #define CONFIG_SYS_MBYTES_SDRAM        (128)    /* 128MB */
 170
 171 /*
 172  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 173  *
 174  * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
 175  *       SDRAM Controller DDR autocalibration values and takes a lot longer
 176  *       to run than Method_B.
 177  * (See the Method_A and Method_B algorithm discription in the file:
 178  *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
 179  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
 180  *
 181  * DDR Autocalibration Method_B is the default.
 182  */
 183 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 184 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
 185 #undef  CONFIG_PPC4xx_DDR_METHOD_A
 186
 187 #define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
 188
 189 /* DDR1/2 SDRAM Device Control Register Data Values */
 190 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
 191                                  SDRAM_RXBAS_SDSZ_128MB | \
 192                                  SDRAM_RXBAS_SDAM_MODE2 | \
 193                                  SDRAM_RXBAS_SDBE_ENABLE)
 194 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
 195 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
 196 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
 197 #define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN | \
 198                                  SDRAM_MCOPT1_4_BANKS | \
 199                                  SDRAM_MCOPT1_DDR2_TYPE | \
 200                                  SDRAM_MCOPT1_QDEP | \
 201                                  SDRAM_MCOPT1_DCOO_DISABLED)
 202 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 203 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
 204                                  SDRAM_MODT_EB0R_ENABLE)
 205 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
 206 #define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON | \
 207                                  SDRAM_CODT_CKLZ_36OHM | \
 208                                  SDRAM_CODT_DQS_1_8_V_DDR2 | \
 209                                  SDRAM_CODT_IO_NMODE)
 210 #define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 211 #define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE | \
 212                 SDRAM_INITPLR_IMWT_ENCODE(80) | \
 213                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 214 #define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE | \
 215                 SDRAM_INITPLR_IMWT_ENCODE(3) | \
 216                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
 217                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
 218                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 219 #define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE | \
 220                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 221                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 222                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
 223                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 224 #define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE | \
 225                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 226                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 227                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
 228                 SDRAM_INITPLR_IMA_ENCODE(0))
 229 #define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE | \
 230                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 231                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 232                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
 233                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 234                                          JEDEC_MA_EMR_RTT_75OHM))
 235 #define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE | \
 236                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 237                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 238                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
 239                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 240                                          JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
 241                                          JEDEC_MA_MR_BLEN_4 | \
 242                                          JEDEC_MA_MR_DLL_RESET))
 243 #define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE | \
 244                 SDRAM_INITPLR_IMWT_ENCODE(3) | \
 245                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
 246                 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
 247                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 248 #define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE | \
 249                 SDRAM_INITPLR_IMWT_ENCODE(26) | \
 250                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 251 #define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE | \
 252                 SDRAM_INITPLR_IMWT_ENCODE(26) | \
 253                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 254 #define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE | \
 255                 SDRAM_INITPLR_IMWT_ENCODE(26) | \
 256                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 257 #define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE | \
 258                 SDRAM_INITPLR_IMWT_ENCODE(26) | \
 259                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 260 #define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE | \
 261                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 262                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 263                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
 264                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 265                                          JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
 266                                          JEDEC_MA_MR_BLEN_4))
 267 #define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE | \
 268                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 269                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 270                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
 271                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
 272                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 273                                          JEDEC_MA_EMR_DQS_DISABLE | \
 274                                          JEDEC_MA_EMR_RTT_DISABLED | \
 275                                          JEDEC_MA_EMR_ODS_NORMAL))
 276 #define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE | \
 277                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 278                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 279                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
 280                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
 281                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 282                                          JEDEC_MA_EMR_DQS_DISABLE | \
 283                                          JEDEC_MA_EMR_RTT_DISABLED | \
 284                                          JEDEC_MA_EMR_ODS_NORMAL))
 285 #define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
 286 #define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
 287 #define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
 288                                  SDRAM_RQDC_RQFD_ENCODE(56))
 289 #define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
 290 #define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 291 #define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO | \
 292                                  SDRAM_DLCR_DLCS_CONT_DONE | \
 293                                  SDRAM_DLCR_DLCV_ENCODE(165))
 294 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
 295 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
 296 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
 297                                  SDRAM_SDTR1_RTW_2_CLK | \
 298                                  SDRAM_SDTR1_WTWO_1_CLK | \
 299                                  SDRAM_SDTR1_RTRO_1_CLK)
 300 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
 301                                  SDRAM_SDTR2_WTR_2_CLK | \
 302                                  SDRAM_SDTR2_XSNR_32_CLK | \
 303                                  SDRAM_SDTR2_WPC_4_CLK | \
 304                                  SDRAM_SDTR2_RPC_2_CLK | \
 305                                  SDRAM_SDTR2_RP_3_CLK | \
 306                                  SDRAM_SDTR2_RRD_2_CLK)
 307 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
 308                                  SDRAM_SDTR3_RC_ENCODE(12) | \
 309                                  SDRAM_SDTR3_XCS | \
 310                                  SDRAM_SDTR3_RFC_ENCODE(21))
 311 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
 312                                  SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
 313                                  SDRAM_MMODE_BLEN_4)
 314 #define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
 315                                  SDRAM_MEMODE_RTT_75OHM)
 316
 317 /*-----------------------------------------------------------------------
 318  * I2C
 319  *----------------------------------------------------------------------*/
 320 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0   400000
 321
 322 #define CONFIG_PCA9698          1       /* NXP PCA9698 */
 323
 324 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN) */
 325 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address */
 326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 327 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 328
 329 /* I2C bootstrap EEPROM */
 330 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x54
 331 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 332 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 333
 334 /* Temp sensor/hwmon/dtt */
 335 #define CONFIG_DTT_LM63         1       /* National LM63 */
 336 #define CONFIG_DTT_SENSORS      { 0x18, 0x4c, 0x4e }    /* Sensor addresses */
 337 #define CONFIG_DTT_PWM_LOOKUPTABLE      \
 338                 { { 40, 10 }, { 43, 13 }, { 46, 16 },  \
 339                   { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
 340 #define CONFIG_DTT_TACH_LIMIT   0xa10
 341
 342 /*-----------------------------------------------------------------------
 343  * Ethernet
 344  *----------------------------------------------------------------------*/
 345 #define CONFIG_M88E1111_PHY     1
 346 #define CONFIG_IBM_EMAC4_V4     1
 347 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 348 #define CONFIG_PHY_ADDR         0x12    /* PHY address, See schematics */
 349
 350 #define CONFIG_PHY_RESET        1       /* reset phy upon startup */
 351 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 352
 353 #define CONFIG_HAS_ETH0         1
 354
 355 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 356 #define CONFIG_PHY1_ADDR        0x13
 357
 358 /* Debug messages for the DDR autocalibration */
 359 #define CONFIG_AUTOCALIB                "silent\0"
 360
 361 /*
 362  * Default environment variables
 363  */
 364 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 365         CONFIG_AMCC_DEF_ENV                                             \
 366         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 367         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 368         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 369         "logversion=2\0"                                                \
 370         "kernel_addr=fc000000\0"                                        \
 371         "fdt_addr=fc1e0000\0"                                           \
 372         "ramdisk_addr=fc200000\0"                                       \
 373         "pciconfighost=1\0"                                             \
 374         "pcie_mode=RP:RP\0"                                             \
 375         ""
 376
 377 /*
 378  * Commands additional to the ones defined in amcc-common.h
 379  */
 380 #define CONFIG_CMD_CHIP_CONFIG
 381 #define CONFIG_CMD_DTT
 382
 383 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 384
 385 /* POST support */
 386 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 387                                  CONFIG_SYS_POST_CPU            | \
 388                                  CONFIG_SYS_POST_ETHER          | \
 389                                  CONFIG_SYS_POST_I2C            | \
 390                                  CONFIG_SYS_POST_MEMORY_ON      | \
 391                                  CONFIG_SYS_POST_UART)
 392
 393 /* Define here the base-addresses of the UARTs to test in POST */
 394 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 395                         CONFIG_SYS_NS16550_COM2 }
 396
 397 #define CONFIG_LOGBUFFER
 398 #define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address */
 399
 400 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 401
 402 /*-----------------------------------------------------------------------
 403  * External Bus Controller (EBC) Setup
 404  *----------------------------------------------------------------------*/
 405
 406 /* Memory Bank 0 (NOR-flash) */
 407 #define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_DISABLED          |       \
 408                                  EBC_BXAP_TWT_ENCODE(11)        |       \
 409                                  EBC_BXAP_BCE_DISABLE           |       \
 410                                  EBC_BXAP_BCT_2TRANS            |       \
 411                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 412                                  EBC_BXAP_OEN_ENCODE(0)         |       \
 413                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 414                                  EBC_BXAP_WBF_ENCODE(2)         |       \
 415                                  EBC_BXAP_TH_ENCODE(2)          |       \
 416                                  EBC_BXAP_RE_DISABLED           |       \
 417                                  EBC_BXAP_SOR_NONDELAYED        |       \
 418                                  EBC_BXAP_BEM_WRITEONLY         |       \
 419                                  EBC_BXAP_PEN_DISABLED)
 420 #define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
 421                                  EBC_BXCR_BS_64MB               |       \
 422                                  EBC_BXCR_BU_RW                 |       \
 423                                  EBC_BXCR_BW_16BIT)
 424
 425 /* Memory Bank 1 (NVRAM/Uart) */
 426 #define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_ENABLED           |       \
 427                                  EBC_BXAP_FWT_ENCODE(8)         |       \
 428                                  EBC_BXAP_BWT_ENCODE(4)         |       \
 429                                  EBC_BXAP_BCE_DISABLE           |       \
 430                                  EBC_BXAP_BCT_2TRANS            |       \
 431                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 432                                  EBC_BXAP_OEN_ENCODE(1)         |       \
 433                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 434                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 435                                  EBC_BXAP_TH_ENCODE(2)          |       \
 436                                  EBC_BXAP_RE_DISABLED           |       \
 437                                  EBC_BXAP_SOR_NONDELAYED        |       \
 438                                  EBC_BXAP_BEM_WRITEONLY         |       \
 439                                  EBC_BXAP_PEN_DISABLED)
 440 #define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
 441                                  EBC_BXCR_BS_1MB                |       \
 442                                  EBC_BXCR_BU_RW                 |       \
 443                                  EBC_BXCR_BW_8BIT)
 444
 445 /* Memory Bank 2 (FPGA) */
 446 #define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 447                                  EBC_BXAP_TWT_ENCODE(5)         |       \
 448                                  EBC_BXAP_BCE_DISABLE           |       \
 449                                  EBC_BXAP_BCT_2TRANS            |       \
 450                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 451                                  EBC_BXAP_OEN_ENCODE(2)         |       \
 452                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 453                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 454                                  EBC_BXAP_TH_ENCODE(0)          |       \
 455                                  EBC_BXAP_RE_DISABLED           |       \
 456                                  EBC_BXAP_SOR_NONDELAYED        |       \
 457                                  EBC_BXAP_BEM_WRITEONLY         |       \
 458                                  EBC_BXAP_PEN_DISABLED)
 459 #define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
 460                                  EBC_BXCR_BS_1MB                |       \
 461                                  EBC_BXCR_BU_RW                 |       \
 462                                  EBC_BXCR_BW_16BIT)
 463
 464 /* Memory Bank 3 (Latches) */
 465 #define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_ENABLED           |       \
 466                                  EBC_BXAP_FWT_ENCODE(8)         |       \
 467                                  EBC_BXAP_BWT_ENCODE(4)         |       \
 468                                  EBC_BXAP_BCE_DISABLE           |       \
 469                                  EBC_BXAP_BCT_2TRANS            |       \
 470                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 471                                  EBC_BXAP_OEN_ENCODE(1)         |       \
 472                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 473                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 474                                  EBC_BXAP_TH_ENCODE(2)          |       \
 475                                  EBC_BXAP_RE_DISABLED           |       \
 476                                  EBC_BXAP_SOR_NONDELAYED        |       \
 477                                  EBC_BXAP_BEM_WRITEONLY         |       \
 478                                  EBC_BXAP_PEN_DISABLED)
 479 #define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
 480                                  EBC_BXCR_BS_1MB                |       \
 481                                  EBC_BXCR_BU_RW                 |       \
 482                                  EBC_BXCR_BW_16BIT)
 483
 484 /* EBC peripherals */
 485
 486 #define CONFIG_SYS_FPGA_BASE(k) \
 487         (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
 488
 489 #define CONFIG_SYS_FPGA_DONE(k) \
 490         (k ? 0x0040 : 0x0080)
 491
 492 #define CONFIG_SYS_FPGA_COUNT           2
 493
 494 #define CONFIG_SYS_FPGA_PTR { \
 495         (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
 496         (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
 497
 498 #define CONFIG_SYS_FPGA_COMMON
 499
 500 #define CONFIG_SYS_LATCH0_RESET         0xffff
 501 #define CONFIG_SYS_LATCH0_BOOT          0xffff
 502 #define CONFIG_SYS_LATCH1_RESET         0xffbf
 503 #define CONFIG_SYS_LATCH1_BOOT          0xffff
 504
 505 /*-----------------------------------------------------------------------
 506  * GPIO Setup
 507  *----------------------------------------------------------------------*/
 508 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out           GPIO */ \
 509 { \
 510 /* GPIO Core 0 */ \
 511 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO0 */ \
 512 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO1 */ \
 513 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO2 */ \
 514 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO3 */ \
 515 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO4 */ \
 516 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO5 */ \
 517 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO6 */ \
 518 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO7 */ \
 519 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO8 */ \
 520 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO9 */ \
 521 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO10 */ \
 522 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO11 */ \
 523 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO12 */ \
 524 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO13 */ \
 525 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO14 */ \
 526 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO15 */ \
 527 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO16 */ \
 528 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO17 */ \
 529 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO18 */ \
 530 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO19 */ \
 531 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0     }, /* GPIO20 */ \
 532 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO21 */ \
 533 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO22 */ \
 534 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO23 */ \
 535 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO24 */ \
 536 {GPIO0_BASE, GPIO_IN,  GPIO_ALT3, GPIO_OUT_0     }, /* GPIO25 */ \
 537 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO26 */ \
 538 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO27 */ \
 539 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO28 */ \
 540 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO29 */ \
 541 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO30 */ \
 542 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO31 */ \
 543 } \
 544 }
 545
 546 #define CONFIG_SYS_GPIO_STARTUP_FINISHED        15
 547 #define CONFIG_SYS_GPIO_STARTUP_FINISHED_N      14
 548
 549 #endif  /* __CONFIG_H */