include/configs/imx8mq_phanbell.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 NXP
   4  */
   5
   6 #ifndef __IMX8M_PHANBELL_H
   7 #define __IMX8M_PHANBELL_H
   8
   9 #include <linux/sizes.h>
  10 #include <asm/arch/imx-regs.h>
  11
  12 #ifdef CONFIG_SPL_BUILD
  13 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  14 #define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
  15
  16 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  17 #define CONFIG_MALLOC_F_ADDR            0x182000
  18 /* For RAW image gives a error info not panic */
  19 #endif
  20
  21 /* ENET Config */
  22 /* ENET1 */
  23 #if defined(CONFIG_CMD_NET)
  24 #define CONFIG_FEC_MXC_PHYADDR          0
  25 #endif
  26
  27 #define CONFIG_MFG_ENV_SETTINGS \
  28         "initrd_addr=0x43800000\0" \
  29         "initrd_high=0xffffffff\0" \
  30
  31 /* Initial environment variables */
  32 #define CFG_EXTRA_ENV_SETTINGS          \
  33         CONFIG_MFG_ENV_SETTINGS \
  34         "script=boot.scr\0" \
  35         "image=Image\0" \
  36         "console=ttymxc0,115200\0" \
  37         "fdt_addr=0x43000000\0"                 \
  38         "fdt_high=0xffffffffffffffff\0"         \
  39         "boot_fdt=try\0" \
  40         "fdt_file=imx8mq-phanbell.dtb\0" \
  41         "initrd_addr=0x43800000\0"              \
  42         "initrd_high=0xffffffffffffffff\0" \
  43         "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  44         "mmcpart=1\0" \
  45         "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
  46         "mmcautodetect=yes\0" \
  47         "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
  48         "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  49         "bootscript=echo Running bootscript from mmc ...; " \
  50                 "source\0" \
  51         "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  52         "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  53         "mmcboot=echo Booting from mmc ...; " \
  54                 "run mmcargs; " \
  55                 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  56                         "if run loadfdt; then " \
  57                                 "booti ${loadaddr} - ${fdt_addr}; " \
  58                         "else " \
  59                                 "echo WARN: Cannot load the DT; " \
  60                         "fi; " \
  61                 "else " \
  62                         "echo wait for boot; " \
  63                 "fi;\0" \
  64         "netargs=setenv bootargs console=${console} " \
  65                 "root=/dev/nfs " \
  66                 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  67         "netboot=echo Booting from net ...; " \
  68                 "run netargs;  " \
  69                 "if test ${ip_dyn} = yes; then " \
  70                         "setenv get_cmd dhcp; " \
  71                 "else " \
  72                         "setenv get_cmd tftp; " \
  73                 "fi; " \
  74                 "${get_cmd} ${loadaddr} ${image}; " \
  75                 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  76                         "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  77                                 "booti ${loadaddr} - ${fdt_addr}; " \
  78                         "else " \
  79                                 "echo WARN: Cannot load the DT; " \
  80                         "fi; " \
  81                 "else " \
  82                         "booti; " \
  83                 "fi;\0"
  84
  85 /* Link Definitions */
  86
  87 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
  88 #define CFG_SYS_INIT_RAM_SIZE        0x80000
  89
  90
  91 #define CFG_SYS_SDRAM_BASE           0x40000000
  92 #define PHYS_SDRAM                      0x40000000
  93 #define PHYS_SDRAM_SIZE                 0x40000000 /* 1GB DDR */
  94
  95 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(1)
  96
  97 #define CFG_SYS_FSL_USDHC_NUM   2
  98 #define CFG_SYS_FSL_ESDHC_ADDR       0
  99
 100 #endif