include/configs/imx8mq_cm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __IMX8M_CM_H
   7 #define __IMX8M_CM_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #define CONFIG_SYS_BOOTM_LEN            (32 * SZ_1M)
  14
  15 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  16
  17 #ifdef CONFIG_SPL_BUILD
  18 #define CONFIG_SYS_SPL_MALLOC_START    0x42200000
  19 #define CONFIG_SYS_SPL_MALLOC_SIZE    0x80000   /* 512 KB */
  20 #define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
  21
  22 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  23 #define CONFIG_MALLOC_F_ADDR            0x182000
  24 /* For RAW image gives a error info not panic */
  25 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  26
  27 #endif
  28
  29 /* ENET Config */
  30 /* ENET1 */
  31
  32 #ifndef CONFIG_SPL_BUILD
  33 #define BOOT_TARGET_DEVICES(func) \
  34                 func(MMC, mmc, 0) \
  35                 func(MMC, mmc, 1) \
  36                 func(DHCP, dhcp, na)
  37
  38 #include <config_distro_bootcmd.h>
  39 #endif
  40
  41 /* Initial environment variables */
  42 #define CONFIG_EXTRA_ENV_SETTINGS               \
  43         BOOTENV \
  44         "scriptaddr=0x43500000\0" \
  45         "kernel_addr_r=0x40880000\0" \
  46         "image=Image\0" \
  47         "console=ttymxc0,115200\0" \
  48         "fdt_addr=0x43000000\0"                 \
  49         "boot_fdt=try\0" \
  50         "fdt_file=imx8mq-cm.dtb\0" \
  51         "initrd_addr=0x43800000\0"              \
  52         "bootm_size=0x10000000\0" \
  53         "mmcpart=1\0" \
  54         "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
  55
  56 /* Link Definitions */
  57
  58 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  59 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
  60
  61
  62 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  63 #define PHYS_SDRAM                      0x40000000
  64 #define PHYS_SDRAM_SIZE                                 0x40000000 /* 1 GB DDR */
  65
  66 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(1)
  67
  68 #define CONFIG_SYS_FSL_USDHC_NUM                2
  69 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
  70
  71 #endif