1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2022 Linaro
7 #ifndef __IMX8MP_RSB3720_H
8 #define __IMX8MP_RSB3720_H
10 #include <linux/sizes.h>
11 #include <linux/stringify.h>
12 #include <asm/arch/imx-regs.h>
13 #include <config_distro_bootcmd.h>
15 #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
17 /* GUIDs for capsule updatable firmware images */
18 #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \
19 EFI_GUID(0xb1251e89, 0x384a, 0x4635, 0xa8, 0x06, \
20 0x3a, 0xa0, 0xb0, 0xe9, 0xf9, 0x65)
22 #define IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID \
23 EFI_GUID(0xb5fb6f08, 0xe142, 0x4db1, 0x97, 0xea, \
24 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9)
26 #ifdef CONFIG_SPL_BUILD
27 #define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \
28 * GD_FLG_FULL_MALLOC_INIT \
33 #if defined(CONFIG_NAND_BOOT)
34 #define CONFIG_SPL_NAND_MXS
41 #if defined(CONFIG_CMD_NET)
42 #define CONFIG_FEC_MXC_PHYADDR 4
44 #ifdef CONFIG_DWC_ETH_QOS
45 #define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
48 #define PHY_ANEG_TIMEOUT 20000
52 #if CONFIG_IS_ENABLED(CMD_MMC)
53 # define BOOT_TARGET_MMC(func) \
57 # define BOOT_TARGET_MMC(func)
60 #if CONFIG_IS_ENABLED(CMD_PXE)
61 # define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
63 # define BOOT_TARGET_PXE(func)
66 #if CONFIG_IS_ENABLED(CMD_DHCP)
67 # define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
69 # define BOOT_TARGET_DHCP(func)
72 #define BOOT_TARGET_DEVICES(func) \
73 BOOT_TARGET_MMC(func) \
74 BOOT_TARGET_PXE(func) \
75 BOOT_TARGET_DHCP(func)
77 /* Initial environment variables */
78 #define CONFIG_EXTRA_ENV_SETTINGS \
82 "splashimage=0x50000000\0" \
83 "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
84 "fdt_addr=0x43000000\0" \
85 "fdt_addr_r=0x43000000\0" \
87 "dfu_alt_info=mmc 2=flash-bin raw 0 0x1B00 mmcpart 1\0" \
88 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
89 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
90 "initrd_addr=0x43800000\0" \
91 "bootm_size=0x10000000\0" \
92 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
94 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
95 "mmcautodetect=yes\0" \
96 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
97 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
98 "bootscript=echo Running bootscript from mmc ...; " \
100 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
101 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
102 "kernel_addr_r=0x40480000\0" \
103 "pxefile_addr_r=0x40480000\0" \
104 "ramdisk_addr_r=0x43800000\0" \
105 "mmcboot=echo Booting from mmc ...; " \
107 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
108 "bootm ${loadaddr}; " \
110 "if run loadfdt; then " \
111 "booti ${loadaddr} - ${fdt_addr}; " \
113 "echo WARN: Cannot load the DT; " \
116 "netargs=setenv bootargs ${jh_clk} console=${console} " \
118 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
119 "netboot=echo Booting from net ...; " \
121 "if test ${ip_dyn} = yes; then " \
122 "setenv get_cmd dhcp; " \
124 "setenv get_cmd tftp; " \
126 "${get_cmd} ${loadaddr} ${image}; " \
127 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
128 "bootm ${loadaddr}; " \
130 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
131 "booti ${loadaddr} - ${fdt_addr}; " \
133 "echo WARN: Cannot load the DT; " \
137 /* Link Definitions */
138 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
139 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
142 /* Totally 6GB or 4G DDR */
143 #define CONFIG_SYS_SDRAM_BASE 0x40000000
144 #define PHYS_SDRAM 0x40000000
145 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
146 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
147 #define PHYS_SDRAM_2 0x100000000
148 #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
149 #elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
150 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
151 #define PHYS_SDRAM_2 0xC0000000
152 #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
155 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
157 #define CONFIG_SYS_FSL_USDHC_NUM 2
158 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
160 #ifdef CONFIG_FSL_FSPI
161 #define FSL_FSPI_FLASH_SIZE SZ_32M
162 #define FSL_FSPI_FLASH_NUM 1
163 #define FSPI0_BASE_ADDR 0x30bb0000
164 #define FSPI0_AMBA_BASE 0x0
165 #define CONFIG_FSPI_QUAD_SUPPORT
167 #define CONFIG_SYS_FSL_FSPI_AHB
170 #ifdef CONFIG_NAND_MXS
173 #define CONFIG_SYS_NAND_BASE 0x20000000
174 #endif /* CONFIG_NAND_MXS */
176 #endif /* __IMX8MP_RSB3720_H */