include/configs/imx8mn_var_som.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2021 Collabora Ltd.
   4  */
   5
   6 #ifndef __IMX8MN_VAR_SOM_H
   7 #define __IMX8MN_VAR_SOM_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #define CONFIG_SYS_BOOTM_LEN            (32 * SZ_1M)
  14
  15 #define CONFIG_SYS_MONITOR_LEN          SZ_512K
  16 #define CONFIG_SYS_UBOOT_BASE   \
  17         (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  18
  19 #define CONFIG_SPL_BSS_START_ADDR       0x950000
  20 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  21 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_512K
  22
  23 #define BOOT_TARGET_DEVICES(func) \
  24         func(MMC, mmc, 1) \
  25         func(MMC, mmc, 2) \
  26         func(MMC, mmc, 0) \
  27         func(PXE, pxe, na) \
  28         func(DHCP, dhcp, na) \
  29
  30 #include <config_distro_bootcmd.h>
  31
  32 #define MEM_LAYOUT_ENV_SETTINGS \
  33         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  34         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  35         "ramdisk_addr_r=0x43800000\0" \
  36         "fdt_addr_r=0x43000000\0" \
  37         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  38         "fastboot_partition_alias_all=" \
  39                 __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \
  40         "fastboot_partition_alias_bootloader=" \
  41                 __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \
  42         "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \
  43         "emmc_ack=1\0" \
  44         "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  45
  46 /* Initial environment variables */
  47 #define CONFIG_EXTRA_ENV_SETTINGS \
  48         MEM_LAYOUT_ENV_SETTINGS \
  49         BOOTENV
  50
  51 /* Link Definitions */
  52
  53 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  54 #define CONFIG_SYS_INIT_RAM_SIZE        SZ_512K
  55
  56 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  57 #define PHYS_SDRAM                      0x40000000
  58 #define PHYS_SDRAM_SIZE                 SZ_1G /* 1GB DDR */
  59
  60 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(4)
  61
  62 /* USDHC */
  63 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
  64
  65 #endif /* __IMX8MN_VAR_SOM_H */