include/configs/imx8mm_venice.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 #ifndef __IMX8MM_VENICE_H
   7 #define __IMX8MM_VENICE_H
   8
   9 #include <asm/arch/imx-regs.h>
  10 #include <linux/sizes.h>
  11
  12 #define CONFIG_SPL_MAX_SIZE             (148 * 1024)
  13 #define CONFIG_SYS_MONITOR_LEN          SZ_512K
  14 #define CONFIG_SYS_UBOOT_BASE   \
  15         (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  16
  17 #ifdef CONFIG_SPL_BUILD
  18 #define CONFIG_SPL_STACK                0x920000
  19 #define CONFIG_SPL_BSS_START_ADDR       0x910000
  20 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_8K
  21 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  22 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_1M
  23
  24 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  25 #define CONFIG_MALLOC_F_ADDR            0x930000
  26 /* For RAW image gives a error info not panic */
  27 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  28
  29 #endif
  30
  31 #define MEM_LAYOUT_ENV_SETTINGS \
  32         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  33         "fdt_addr_r=0x50200000\0" \
  34         "scriptaddr=0x50280000\0" \
  35         "ramdisk_addr_r=0x50300000\0" \
  36         "kernel_comp_addr_r=0x40200000\0"
  37
  38 /* Enable Distro Boot */
  39 #ifndef CONFIG_SPL_BUILD
  40 #define BOOT_TARGET_DEVICES(func) \
  41         func(MMC, mmc, 1) \
  42         func(MMC, mmc, 2) \
  43         func(USB, usb, 0) \
  44         func(USB, usb, 1) \
  45         func(DHCP, dhcp, na)
  46 #include <config_distro_bootcmd.h>
  47 #else
  48 #define BOOTENV
  49 #endif
  50
  51 /* Initial environment variables */
  52 #define CONFIG_EXTRA_ENV_SETTINGS \
  53         BOOTENV \
  54         MEM_LAYOUT_ENV_SETTINGS \
  55         "script=boot.scr\0" \
  56         "bootm_size=0x10000000\0" \
  57         "dev=2\0" \
  58         "preboot=gsc wd-disable\0" \
  59         "console=ttymxc1,115200\0" \
  60         "update_firmware=" \
  61                 "tftpboot $loadaddr $image && " \
  62                 "setexpr blkcnt $filesize + 0x1ff && " \
  63                 "setexpr blkcnt $blkcnt / 0x200 && " \
  64                 "mmc dev $dev && " \
  65                 "mmc write $loadaddr 0x42 $blkcnt\0" \
  66         "loadfdt=" \
  67                 "if $fsload $fdt_addr_r $dir/$fdt_file1; " \
  68                         "then echo loaded $fdt_file1; " \
  69                 "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \
  70                         "then echo loaded $fdt_file2; " \
  71                 "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \
  72                         "then echo loaded $fdt_file3; " \
  73                 "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \
  74                         "then echo loaded $fdt_file4; " \
  75                 "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \
  76                         "then echo loaded $fdt_file5; " \
  77                 "fi\0" \
  78         "boot_net=" \
  79                 "setenv fsload tftpboot; " \
  80                 "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \
  81                 "booti $kernel_addr_r - $fdt_addr_r\0" \
  82         "update_rootfs=" \
  83                 "tftpboot $loadaddr $image && " \
  84                 "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
  85         "update_all=" \
  86                 "tftpboot $loadaddr $image && " \
  87                 "gzwrite mmc $dev $loadaddr $filesize\0" \
  88         "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
  89
  90 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  91 #define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
  92 #define CONFIG_SYS_INIT_SP_OFFSET \
  93         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  94 #define CONFIG_SYS_INIT_SP_ADDR \
  95         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  96
  97 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  98
  99 /* SDRAM configuration */
 100 #define PHYS_SDRAM                      0x40000000
 101 #define PHYS_SDRAM_SIZE                 SZ_4G
 102 #define CONFIG_SYS_BOOTM_LEN            SZ_256M
 103
 104 /* UART */
 105 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(2)
 106
 107 /* FEC */
 108 #define CONFIG_FEC_MXC_PHYADDR          0
 109 #define FEC_QUIRK_ENET_MAC
 110
 111 #endif