include/configs/imx8mm_venice.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 #ifndef __IMX8MM_VENICE_H
   7 #define __IMX8MM_VENICE_H
   8
   9 #include <asm/arch/imx-regs.h>
  10 #include <linux/sizes.h>
  11
  12 #define CONFIG_SYS_MONITOR_LEN          SZ_512K
  13 #define CONFIG_SYS_UBOOT_BASE   \
  14         (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  15
  16 #ifdef CONFIG_SPL_BUILD
  17 #define CONFIG_SPL_STACK                0x920000
  18 #define CONFIG_SPL_BSS_START_ADDR       0x910000
  19 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_8K
  20 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  21 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_1M
  22
  23 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  24 #define CONFIG_MALLOC_F_ADDR            0x930000
  25 /* For RAW image gives a error info not panic */
  26 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  27
  28 #endif
  29
  30 #define MEM_LAYOUT_ENV_SETTINGS \
  31         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  32         "fdt_addr_r=0x50200000\0" \
  33         "scriptaddr=0x50280000\0" \
  34         "ramdisk_addr_r=0x50300000\0" \
  35         "kernel_comp_addr_r=0x40200000\0"
  36
  37 /* Enable Distro Boot */
  38 #ifndef CONFIG_SPL_BUILD
  39 #define BOOT_TARGET_DEVICES(func) \
  40         func(MMC, mmc, 1) \
  41         func(MMC, mmc, 2) \
  42         func(USB, usb, 0) \
  43         func(USB, usb, 1) \
  44         func(DHCP, dhcp, na)
  45 #include <config_distro_bootcmd.h>
  46 #else
  47 #define BOOTENV
  48 #endif
  49
  50 /* Initial environment variables */
  51 #define CONFIG_EXTRA_ENV_SETTINGS \
  52         BOOTENV \
  53         MEM_LAYOUT_ENV_SETTINGS \
  54         "script=boot.scr\0" \
  55         "bootm_size=0x10000000\0" \
  56         "dev=2\0" \
  57         "preboot=gsc wd-disable\0" \
  58         "console=ttymxc1,115200\0" \
  59         "update_firmware=" \
  60                 "tftpboot $loadaddr $image && " \
  61                 "setexpr blkcnt $filesize + 0x1ff && " \
  62                 "setexpr blkcnt $blkcnt / 0x200 && " \
  63                 "mmc dev $dev && " \
  64                 "mmc write $loadaddr 0x42 $blkcnt\0" \
  65         "loadfdt=" \
  66                 "if $fsload $fdt_addr_r $dir/$fdt_file1; " \
  67                         "then echo loaded $fdt_file1; " \
  68                 "elif $fsload $fdt_addr_r $dir/$fdt_file2; " \
  69                         "then echo loaded $fdt_file2; " \
  70                 "elif $fsload $fdt_addr_r $dir/$fdt_file3; " \
  71                         "then echo loaded $fdt_file3; " \
  72                 "elif $fsload $fdt_addr_r $dir/$fdt_file4; " \
  73                         "then echo loaded $fdt_file4; " \
  74                 "elif $fsload $fdt_addr_r $dir/$fdt_file5; " \
  75                         "then echo loaded $fdt_file5; " \
  76                 "fi\0" \
  77         "boot_net=" \
  78                 "setenv fsload tftpboot; " \
  79                 "run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \
  80                 "booti $kernel_addr_r - $fdt_addr_r\0" \
  81         "update_rootfs=" \
  82                 "tftpboot $loadaddr $image && " \
  83                 "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
  84         "update_all=" \
  85                 "tftpboot $loadaddr $image && " \
  86                 "gzwrite mmc $dev $loadaddr $filesize\0" \
  87         "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
  88
  89 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  90 #define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
  91 #define CONFIG_SYS_INIT_SP_OFFSET \
  92         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  93 #define CONFIG_SYS_INIT_SP_ADDR \
  94         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  95
  96 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  97
  98 /* SDRAM configuration */
  99 #define PHYS_SDRAM                      0x40000000
 100 #define PHYS_SDRAM_SIZE                 SZ_4G
 101 #define CONFIG_SYS_BOOTM_LEN            SZ_256M
 102
 103 /* UART */
 104 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(2)
 105
 106 /* FEC */
 107 #define CONFIG_FEC_MXC_PHYADDR          0
 108 #define FEC_QUIRK_ENET_MAC
 109
 110 #endif