include/configs/imx8mm_evk.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #ifndef __IMX8MM_EVK_H
   7 #define __IMX8MM_EVK_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #define CONFIG_SYS_BOOTM_LEN            (32 * SZ_1M)
  14 #define CONFIG_SPL_MAX_SIZE             (148 * 1024)
  15 #define CONFIG_SYS_MONITOR_LEN          SZ_512K
  16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  18 #define CONFIG_SYS_UBOOT_BASE   \
  19         (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  20
  21 #ifdef CONFIG_SPL_BUILD
  22 #define CONFIG_SPL_STACK                0x920000
  23 #define CONFIG_SPL_BSS_START_ADDR       0x910000
  24 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_8K   /* 8 KB */
  25 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  26 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_512K /* 512 KB */
  27
  28 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  29 #define CONFIG_MALLOC_F_ADDR            0x930000
  30 /* For RAW image gives a error info not panic */
  31 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  32
  33 #endif
  34
  35 #ifndef CONFIG_SPL_BUILD
  36 #define BOOT_TARGET_DEVICES(func) \
  37         func(MMC, mmc, 1) \
  38         func(MMC, mmc, 2) \
  39         func(DHCP, dhcp, na)
  40
  41 #include <config_distro_bootcmd.h>
  42 #endif
  43
  44 /* Initial environment variables */
  45 #define CONFIG_EXTRA_ENV_SETTINGS               \
  46         BOOTENV \
  47         "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
  48         "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  49         "image=Image\0" \
  50         "console=ttymxc1,115200\0" \
  51         "fdt_addr_r=0x43000000\0"                       \
  52         "boot_fit=no\0" \
  53         "fdtfile=imx8mm-evk.dtb\0" \
  54         "initrd_addr=0x43800000\0"              \
  55         "bootm_size=0x10000000\0" \
  56         "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  57         "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  58
  59 /* Link Definitions */
  60 #define CONFIG_LOADADDR                 0x40480000
  61
  62 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  63
  64 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  65 #define CONFIG_SYS_INIT_RAM_SIZE        0x200000
  66 #define CONFIG_SYS_INIT_SP_OFFSET \
  67         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  68 #define CONFIG_SYS_INIT_SP_ADDR \
  69         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  70
  71 #define CONFIG_MMCROOT                  "/dev/mmcblk1p2"  /* USDHC2 */
  72
  73 /* Size of malloc() pool */
  74 #define CONFIG_SYS_MALLOC_LEN           SZ_32M
  75
  76 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  77 #define PHYS_SDRAM                      0x40000000
  78 #define PHYS_SDRAM_SIZE                 0x80000000 /* 2GB DDR */
  79
  80 #define CONFIG_MXC_UART_BASE            UART2_BASE_ADDR
  81
  82 /* Monitor Command Prompt */
  83 #define CONFIG_SYS_CBSIZE               2048
  84 #define CONFIG_SYS_MAXARGS              64
  85 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  86 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  87                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  88
  89 /* USDHC */
  90 #define CONFIG_FSL_USDHC
  91
  92 #define CONFIG_SYS_FSL_USDHC_NUM        2
  93 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
  94
  95 #define CONFIG_SYS_MMC_IMG_LOAD_PART    1
  96
  97 #define CONFIG_ETHPRIME                 "FEC"
  98
  99 #define CONFIG_FEC_XCV_TYPE             RGMII
 100 #define CONFIG_FEC_MXC_PHYADDR          0
 101 #define FEC_QUIRK_ENET_MAC
 102
 103 #define IMX_FEC_BASE                    0x30BE0000
 104
 105 #endif