e759db2ff2fbc1f1fed5cd5b8ad4baa253de214e
[platform/kernel/u-boot.git] / include / configs / ids8313.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2013
4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5  *
6  * Based on:
7  * Copyright (c) 2011 IDS GmbH, Germany
8  * Sergej Stepanov <ste@ids.de>
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #include <linux/stringify.h>
15
16 /*
17  * High Level Configuration Options
18  */
19 #define CONFIG_BOOT_RETRY_TIME          900
20 #define CONFIG_BOOT_RETRY_MIN           30
21 #define CONFIG_RESET_TO_RETRY
22
23 #define CONFIG_SYS_SICRH        0x00000000
24 #define CONFIG_SYS_SICRL        (SICRL_LBC | SICRL_SPI_D)
25
26 #define CONFIG_HWCONFIG
27
28 /*
29  * Definitions for initial stack pointer and data area (in DCACHE )
30  */
31 #define CONFIG_SYS_INIT_RAM_LOCK
32 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
33 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* End of used area in DPRAM */
34 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
35 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
36                                          - CONFIG_SYS_GBL_DATA_SIZE)
37 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
38
39 /*
40  * Internal Definitions
41  */
42 /*
43  * DDR Setup
44  */
45 #define CONFIG_SYS_SDRAM_BASE           0x00000000
46
47 /*
48  * Manually set up DDR parameters,
49  * as this board has not the SPD connected to I2C.
50  */
51 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
52 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN |\
53                                          0x00010000 |\
54                                          CSCONFIG_ROW_BIT_13 |\
55                                          CSCONFIG_COL_BIT_10)
56
57 #define CONFIG_SYS_DDR_CONFIG_256       (CONFIG_SYS_DDR_CONFIG | \
58                                          CSCONFIG_BANK_BIT_3)
59
60 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16)       /* ext refrec */
61 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
62                                 (3 << TIMING_CFG0_WRT_SHIFT) |\
63                                 (3 << TIMING_CFG0_RRT_SHIFT) |\
64                                 (3 << TIMING_CFG0_WWT_SHIFT) |\
65                                 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
66                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
67                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
68                                 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
69 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
70                                 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
71                                 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
72                                 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
73                                 (4 << TIMING_CFG1_REFREC_SHIFT) |\
74                                 (4 << TIMING_CFG1_WRREC_SHIFT) |\
75                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
76                                 (2 << TIMING_CFG1_WRTORD_SHIFT))
77 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
78                                 (5 << TIMING_CFG2_CPO_SHIFT) |\
79                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
80                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
81                                 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
82                                 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
83                                 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
84
85 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
86                                 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
87
88 #define CONFIG_SYS_SDRAM_CFG            (SDRAM_CFG_SREN |\
89                                          SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
90                                          SDRAM_CFG_DBW_32 |\
91                                          SDRAM_CFG_SDRAM_TYPE_DDR2)
92
93 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
94 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
95                                          (0x0242 << SDRAM_MODE_SD_SHIFT))
96 #define CONFIG_SYS_DDR_MODE_2           0x00000000
97 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
98 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
99                                          DDRCDR_PZ_NOMZ |\
100                                          DDRCDR_NZ_NOMZ |\
101                                          DDRCDR_ODT |\
102                                          DDRCDR_M_ODR |\
103                                          DDRCDR_Q_DRN)
104
105 /*
106  * on-board devices
107  */
108 #define CONFIG_TSEC1
109 #define CONFIG_TSEC2
110
111 /*
112  * NOR FLASH setup
113  */
114 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
115 #define CONFIG_FLASH_SHOW_PROGRESS      50
116
117 #define CONFIG_SYS_FLASH_BASE           0xFF800000
118 #define CONFIG_SYS_FLASH_SIZE           8
119
120
121 #define CONFIG_SYS_MAX_FLASH_BANKS      1
122 #define CONFIG_SYS_MAX_FLASH_SECT       128
123
124 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
125 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
126
127 /*
128  * NAND FLASH setup
129  */
130 #define CONFIG_SYS_NAND_BASE            0xE1000000
131 #define CONFIG_SYS_MAX_NAND_DEVICE      1
132 #define CONFIG_SYS_NAND_MAX_CHIPS       1
133 #define CONFIG_NAND_FSL_ELBC
134 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)
135 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
136 #define NAND_CACHE_PAGES                64
137
138
139 /*
140  * MRAM setup
141  */
142 #define CONFIG_SYS_MRAM_BASE            0xE2000000
143 #define CONFIG_SYS_MRAM_SIZE            0x20000 /* 128 Kb */
144
145 #define CONFIG_SYS_OR_TIMING_MRAM
146
147
148 /*
149  * CPLD setup
150  */
151 #define CONFIG_SYS_CPLD_BASE            0xE3000000
152 #define CONFIG_SYS_CPLD_SIZE            0x8000
153
154 #define CONFIG_SYS_OR_TIMING_MRAM
155
156
157 /*
158  * HW-Watchdog
159  */
160 #define CONFIG_WATCHDOG         1
161 #define CONFIG_SYS_WATCHDOG_VALUE       0xFFFF
162
163 /*
164  * I2C setup
165  */
166 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
167
168 /*
169  * Ethernet setup
170  */
171 #ifdef CONFIG_TSEC1
172 #define CONFIG_HAS_ETH0
173 #define CONFIG_TSEC1_NAME               "TSEC0"
174 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
175 #define TSEC1_PHY_ADDR                  0x1
176 #define TSEC1_FLAGS                     TSEC_GIGABIT
177 #define TSEC1_PHYIDX                    0
178 #endif
179
180 #ifdef CONFIG_TSEC2
181 #define CONFIG_HAS_ETH1
182 #define CONFIG_TSEC2_NAME               "TSEC1"
183 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
184 #define TSEC2_PHY_ADDR                  0x3
185 #define TSEC2_FLAGS                     TSEC_GIGABIT
186 #define TSEC2_PHYIDX                    0
187 #endif
188 #define CONFIG_ETHPRIME         "TSEC1"
189
190 /*
191  * Serial Port
192  */
193 #define CONFIG_SYS_NS16550_SERIAL
194 #define CONFIG_SYS_NS16550_REG_SIZE     1
195
196 #define CONFIG_SYS_BAUDRATE_TABLE       \
197         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
200 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
201
202 #define CONFIG_HAS_FSL_DR_USB
203 #define CONFIG_SYS_SCCR_USBDRCM 3
204
205 /*
206  * U-Boot environment setup
207  */
208 #define CONFIG_BOOTP_BOOTFILESIZE
209
210 /*
211  * The reserved memory
212  */
213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
214 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
215
216 /*
217  * Environment Configuration
218  */
219
220 #define CONFIG_NETDEV                   eth1
221 #define CONFIG_HOSTNAME         "ids8313"
222 #define CONFIG_ROOTPATH         "/opt/eldk-4.2/ppc_6xx"
223 #define CONFIG_BOOTFILE         "ids8313/uImage"
224 #define CONFIG_UBOOTPATH                "ids8313/u-boot.bin"
225 #define CONFIG_FDTFILE                  "ids8313/ids8313.dtb"
226 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
227
228 /* Initial Memory map for Linux*/
229 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
230
231 /*
232  * Miscellaneous configurable options
233  */
234 #define CONFIG_SYS_CBSIZE               1024
235 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
236
237 #define CONFIG_LOADS_ECHO
238 #define CONFIG_TIMESTAMP
239 #define CONFIG_BOOTCOMMAND              "run boot_cramfs"
240 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
241
242 #define CONFIG_JFFS2_NAND
243 #define CONFIG_JFFS2_DEV                "0"
244
245 /* mtdparts command line support */
246
247 #define CONFIG_EXTRA_ENV_SETTINGS \
248         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
249         "ethprime=TSEC1\0"                                              \
250         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
251         "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
252                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
253                 " +${filesize}; "                                       \
254                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
255                 " +${filesize}; "                                       \
256                 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
257                 " ${filesize}; "                                        \
258                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
259                 " +${filesize}; "                                       \
260                 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
261                 " ${filesize}\0"                                        \
262         "console=ttyS0\0"                                               \
263         "fdtaddr=0x780000\0"                                            \
264         "kernel_addr=ff800000\0"                                        \
265         "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
266         "setbootargs=setenv bootargs "                                  \
267                 "root=${rootdev} rw console=${console},"                \
268                         "${baudrate} ${othbootargs}\0"                  \
269         "setipargs=setenv bootargs root=${rootdev} rw "                 \
270                         "nfsroot=${serverip}:${rootpath} "              \
271                         "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
272                         "${netmask}:${hostname}:${netdev}:off "         \
273                         "console=${console},${baudrate} ${othbootargs}\0" \
274         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
275         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                                    \
276         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                                \
277         "\0"
278
279 #define NFSBOOTCOMMAND                                          \
280         "setenv rootdev /dev/nfs;"                                      \
281         "run setipargs;run addmtd;"                                     \
282         "tftp ${loadaddr} ${bootfile};"                         \
283         "tftp ${fdtaddr} ${fdtfile};"                                   \
284         "fdt addr ${fdtaddr};"                                          \
285         "bootm ${loadaddr} - ${fdtaddr}"
286
287 /* UBI Support */
288
289 #endif  /* __CONFIG_H */