include/configs/ids8313.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2013
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (c) 2011 IDS GmbH, Germany
   8  * Sergej Stepanov <ste@ids.de>
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include <linux/stringify.h>
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19
  20 #define CONFIG_SYS_SICRH        0x00000000
  21 #define CONFIG_SYS_SICRL        (SICRL_LBC | SICRL_SPI_D)
  22
  23 #define CONFIG_HWCONFIG
  24
  25 /*
  26  * Definitions for initial stack pointer and data area (in DCACHE )
  27  */
  28 #define CONFIG_SYS_INIT_RAM_LOCK
  29 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
  30 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* End of used area in DPRAM */
  31 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
  32 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
  33                                          - CONFIG_SYS_GBL_DATA_SIZE)
  34 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  35
  36 /*
  37  * Internal Definitions
  38  */
  39 /*
  40  * DDR Setup
  41  */
  42 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  43
  44 /*
  45  * Manually set up DDR parameters,
  46  * as this board has not the SPD connected to I2C.
  47  */
  48 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  49 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN |\
  50                                          0x00010000 |\
  51                                          CSCONFIG_ROW_BIT_13 |\
  52                                          CSCONFIG_COL_BIT_10)
  53
  54 #define CONFIG_SYS_DDR_CONFIG_256       (CONFIG_SYS_DDR_CONFIG | \
  55                                          CSCONFIG_BANK_BIT_3)
  56
  57 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16)       /* ext refrec */
  58 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
  59                                 (3 << TIMING_CFG0_WRT_SHIFT) |\
  60                                 (3 << TIMING_CFG0_RRT_SHIFT) |\
  61                                 (3 << TIMING_CFG0_WWT_SHIFT) |\
  62                                 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
  63                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
  64                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  65                                 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  66 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
  67                                 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
  68                                 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
  69                                 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
  70                                 (4 << TIMING_CFG1_REFREC_SHIFT) |\
  71                                 (4 << TIMING_CFG1_WRREC_SHIFT) |\
  72                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
  73                                 (2 << TIMING_CFG1_WRTORD_SHIFT))
  74 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
  75                                 (5 << TIMING_CFG2_CPO_SHIFT) |\
  76                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
  77                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
  78                                 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
  79                                 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
  80                                 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  81
  82 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
  83                                 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  84
  85 #define CONFIG_SYS_SDRAM_CFG            (SDRAM_CFG_SREN |\
  86                                          SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
  87                                          SDRAM_CFG_DBW_32 |\
  88                                          SDRAM_CFG_SDRAM_TYPE_DDR2)
  89
  90 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
  91 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
  92                                          (0x0242 << SDRAM_MODE_SD_SHIFT))
  93 #define CONFIG_SYS_DDR_MODE_2           0x00000000
  94 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
  95 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
  96                                          DDRCDR_PZ_NOMZ |\
  97                                          DDRCDR_NZ_NOMZ |\
  98                                          DDRCDR_ODT |\
  99                                          DDRCDR_M_ODR |\
 100                                          DDRCDR_Q_DRN)
 101
 102 /*
 103  * on-board devices
 104  */
 105 #define CONFIG_TSEC1
 106 #define CONFIG_TSEC2
 107
 108 /*
 109  * NOR FLASH setup
 110  */
 111 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
 112 #define CONFIG_FLASH_SHOW_PROGRESS      50
 113
 114 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 115 #define CONFIG_SYS_FLASH_SIZE           8
 116
 117
 118 #define CONFIG_SYS_MAX_FLASH_SECT       128
 119
 120 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
 121 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 122
 123 /*
 124  * NAND FLASH setup
 125  */
 126 #define CONFIG_SYS_NAND_BASE            0xE1000000
 127 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 128 #define NAND_CACHE_PAGES                64
 129
 130
 131 /*
 132  * MRAM setup
 133  */
 134 #define CONFIG_SYS_MRAM_BASE            0xE2000000
 135 #define CONFIG_SYS_MRAM_SIZE            0x20000 /* 128 Kb */
 136
 137 #define CONFIG_SYS_OR_TIMING_MRAM
 138
 139
 140 /*
 141  * CPLD setup
 142  */
 143 #define CONFIG_SYS_CPLD_BASE            0xE3000000
 144 #define CONFIG_SYS_CPLD_SIZE            0x8000
 145
 146 #define CONFIG_SYS_OR_TIMING_MRAM
 147
 148
 149 /*
 150  * HW-Watchdog
 151  */
 152 #define CONFIG_SYS_WATCHDOG_VALUE       0xFFFF
 153
 154 /*
 155  * I2C setup
 156  */
 157 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 158
 159 /*
 160  * Ethernet setup
 161  */
 162 #ifdef CONFIG_TSEC1
 163 #define CONFIG_TSEC1_NAME               "TSEC0"
 164 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 165 #define TSEC1_PHY_ADDR                  0x1
 166 #define TSEC1_FLAGS                     TSEC_GIGABIT
 167 #define TSEC1_PHYIDX                    0
 168 #endif
 169
 170 #ifdef CONFIG_TSEC2
 171 #define CONFIG_TSEC2_NAME               "TSEC1"
 172 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 173 #define TSEC2_PHY_ADDR                  0x3
 174 #define TSEC2_FLAGS                     TSEC_GIGABIT
 175 #define TSEC2_PHYIDX                    0
 176 #endif
 177
 178 /*
 179  * Serial Port
 180  */
 181 #define CONFIG_SYS_NS16550_SERIAL
 182 #define CONFIG_SYS_NS16550_REG_SIZE     1
 183
 184 #define CONFIG_SYS_BAUDRATE_TABLE       \
 185         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 186 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 187 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 188 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
 189
 190 #define CONFIG_HAS_FSL_DR_USB
 191 #define CONFIG_SYS_SCCR_USBDRCM 3
 192
 193 /*
 194  * U-Boot environment setup
 195  */
 196
 197 /*
 198  * The reserved memory
 199  */
 200 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 201
 202 /*
 203  * Environment Configuration
 204  */
 205
 206 #define CONFIG_NETDEV                   eth1
 207 #define CONFIG_HOSTNAME         "ids8313"
 208 #define CONFIG_ROOTPATH         "/opt/eldk-4.2/ppc_6xx"
 209 #define CONFIG_UBOOTPATH                "ids8313/u-boot.bin"
 210 #define CONFIG_FDTFILE                  "ids8313/ids8313.dtb"
 211 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
 212
 213 /* Initial Memory map for Linux*/
 214 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 215
 216 /*
 217  * Miscellaneous configurable options
 218  */
 219
 220 #define CONFIG_LOADS_ECHO
 221 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 222
 223 /* mtdparts command line support */
 224
 225 #define CONFIG_EXTRA_ENV_SETTINGS \
 226         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 227         "ethprime=TSEC1\0"                                              \
 228         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 229         "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
 230                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 231                 " +${filesize}; "                                       \
 232                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 233                 " +${filesize}; "                                       \
 234                 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
 235                 " ${filesize}; "                                        \
 236                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 237                 " +${filesize}; "                                       \
 238                 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
 239                 " ${filesize}\0"                                        \
 240         "console=ttyS0\0"                                               \
 241         "fdtaddr=0x780000\0"                                            \
 242         "kernel_addr=ff800000\0"                                        \
 243         "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
 244         "setbootargs=setenv bootargs "                                  \
 245                 "root=${rootdev} rw console=${console},"                \
 246                         "${baudrate} ${othbootargs}\0"                  \
 247         "setipargs=setenv bootargs root=${rootdev} rw "                 \
 248                         "nfsroot=${serverip}:${rootpath} "              \
 249                         "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
 250                         "${netmask}:${hostname}:${netdev}:off "         \
 251                         "console=${console},${baudrate} ${othbootargs}\0" \
 252         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 253         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                                    \
 254         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                                \
 255         "\0"
 256
 257 /* UBI Support */
 258
 259 #endif  /* __CONFIG_H */