1 /* Configuration header file for Gaisler Research AB's Template
2 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
3 * Development board Stratix II edition, with the FPGA device
6 * (C) Copyright 2003-2005
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
12 * SPDX-License-Identifier: GPL-2.0+
19 * High Level Configuration Options
23 /* Altera NIOS Development board, Stratix II board */
24 #define CONFIG_GR_EP2S60 1
26 /* CPU / AMBA BUS configuration */
27 #define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
29 /* Define this is the GR-2S60-MEZZ mezzanine is available and you
30 * want to use the USB and GRETH functionality of the board
40 * Serial console configuration
42 #define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
43 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
46 #define CONFIG_DOS_PARTITION
47 #define CONFIG_ISO_PARTITION
52 #define CONFIG_CMD_REGINFO
53 #define CONFIG_CMD_DIAG
54 #define CONFIG_CMD_IRQ
58 #define CONFIG_USB_UHCI
59 /* Enable needed helper functions */
66 #define CONFIG_PREBOOT "echo;" \
67 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
70 #undef CONFIG_BOOTARGS
72 #define CONFIG_EXTRA_ENV_SETTINGS \
74 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
75 "nfsroot=${serverip}:${rootpath}\0" \
76 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
77 "addip=setenv bootargs ${bootargs} " \
78 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
79 ":${hostname}:${netdev}:off panic=1\0" \
80 "flash_nfs=run nfsargs addip;" \
81 "bootm ${kernel_addr}\0" \
82 "flash_self=run ramargs addip;" \
83 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
84 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
85 "scratch=40800000\0" \
86 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
87 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
90 #define CONFIG_NETMASK 255.255.255.0
91 #define CONFIG_GATEWAYIP 192.168.0.1
92 #define CONFIG_SERVERIP 192.168.0.20
93 #define CONFIG_IPADDR 192.168.0.207
94 #define CONFIG_ROOTPATH "/export/rootfs"
95 #define CONFIG_HOSTNAME ml401
96 #define CONFIG_BOOTFILE "/uImage"
98 #define CONFIG_BOOTCOMMAND "run flash_self"
103 * |--------------------------------|
104 * | 0x00000000 Text & Data & BSS | *
106 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
107 * | UNUSED / Growth | * 256kb
108 * |--------------------------------|
109 * | 0x00050000 Base custom area | *
111 * | | * Rest of Flash
112 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
113 * | END-0x00008000 Environment | * 32kb
114 * |--------------------------------|
119 * |--------------------------------|
120 * | UNUSED / scratch area |
125 * |--------------------------------|
126 * | Monitor .Text / .DATA / .BSS | * 512kb
128 * |--------------------------------|
129 * | Monitor Malloc | * 128kb (contains relocated environment)
130 * |--------------------------------|
131 * | Monitor/kernel STACK | * 64kb
132 * |--------------------------------|
133 * | Page Table for MMU systems | * 2k
134 * |--------------------------------|
135 * | PROM Code accessed from Linux | * 6kb-128b
136 * |--------------------------------|
137 * | Global data (avail from kernel)| * 128b
138 * |--------------------------------|
143 * Flash configuration (8,16 or 32 MB)
144 * TEXT base always at 0xFFF00000
145 * ENV_ADDR always at 0xFFF40000
146 * FLASH_BASE at 0xFC000000 for 64 MB
147 * 0xFE000000 for 32 MB
148 * 0xFF000000 for 16 MB
149 * 0xFF800000 for 8 MB
151 /*#define CONFIG_SYS_NO_FLASH 1*/
152 #define CONFIG_SYS_FLASH_BASE 0x00000000
153 #define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
155 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
156 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
159 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
160 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
161 #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
162 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
163 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
166 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
167 #define CONFIG_FLASH_CFI_DRIVER
168 #define CONFIG_SYS_FLASH_CFI
169 /* Bypass cache when reading regs from flash memory */
170 #define CONFIG_SYS_FLASH_CFI_BYPASS_READ
171 /* Buffered writes (32byte/go) instead of single accesses */
172 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
175 * Environment settings
177 /*#define CONFIG_ENV_IS_NOWHERE 1*/
178 #define CONFIG_ENV_IS_IN_FLASH 1
179 /* CONFIG_ENV_ADDR need to be at sector boundary */
180 #define CONFIG_ENV_SIZE 0x8000
181 #define CONFIG_ENV_SECT_SIZE 0x20000
182 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
183 #define CONFIG_ENV_OVERWRITE 1
188 #define CONFIG_SYS_SDRAM_BASE 0x40000000
189 #define CONFIG_SYS_SDRAM_SIZE 0x02000000
190 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
192 /* no SRAM available */
193 #undef CONFIG_SYS_SRAM_BASE
194 #undef CONFIG_SYS_SRAM_SIZE
196 #define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
197 #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
198 #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
200 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
202 #define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
203 #define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
205 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
206 #define CONFIG_SYS_STACK_SIZE (0x10000-32)
208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
209 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
210 # define CONFIG_SYS_RAMBOOT 1
213 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
214 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
215 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
217 #define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
218 #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
220 /* relocated monitor area */
221 #define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
222 #define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
224 /* make un relocated address from relocated address */
225 #define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
228 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
229 * with a PHY is attached the GRETH can be used on this board.
230 * Define USE_GRETH in order to use the mezzanine provided PHY with the
231 * onchip GRETH network MAC, note that this is not supported by the
236 /* USE SMC91C111 MAC */
237 #define CONFIG_SMC91111 1
238 #define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
239 #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
240 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
241 /*#define CONFIG_SHOW_ACTIVITY*/
242 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
246 /* USE GRETH Ethernet Driver */
247 #define CONFIG_GRETH 1
250 #define CONFIG_PHY_ADDR 0x00
253 * Miscellaneous configurable options
255 #define CONFIG_SYS_LONGHELP /* undef to save memory */
256 #if defined(CONFIG_CMD_KGDB)
257 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
259 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
261 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
262 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
263 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
265 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
266 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
268 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
270 /*-----------------------------------------------------------------------
272 *-----------------------------------------------------------------------
274 #define CONFIG_USB_CLOCK 0x0001BBBB
275 #define CONFIG_USB_CONFIG 0x00005000
277 /***** Gaisler GRLIB IP-Cores Config ********/
279 #define CONFIG_SYS_GRLIB_SDRAM 0
281 /* No SDRAM Configuration */
282 #undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
284 /* See, GRLIB Docs (grip.pdf) on how to set up
285 * These the memory controller registers.
287 #define CONFIG_SYS_GRLIB_ESA_MCTRL1
288 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
289 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
290 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
292 /* GRLIB FT-MCTRL configuration */
293 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
294 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
295 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
296 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
299 #define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
300 #define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
302 /* no DDR2 Controller */
303 #undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
305 /* default kernel command line */
306 #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
308 #endif /* __CONFIG_H */