include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 /*----------------------------------------------------------------------*
  12  * High Level Configuration Options (easy to change)                    *
  13  *----------------------------------------------------------------------*/
  14
  15 #define CFG_SYS_UART_PORT               (0)
  16
  17 /*----------------------------------------------------------------------*
  18  * Options                                                              *
  19  *----------------------------------------------------------------------*/
  20
  21 #define STATUS_LED_ACTIVE               0
  22
  23 /*----------------------------------------------------------------------*
  24  * Configuration for environment                                        *
  25  * Environment is in the second sector of the first 256k of flash       *
  26  *----------------------------------------------------------------------*/
  27
  28 /*#define CFG_SYS_DRAM_TEST             1 */
  29 #undef CFG_SYS_DRAM_TEST
  30
  31 /*----------------------------------------------------------------------*
  32  * Clock and PLL Configuration                                          *
  33  *----------------------------------------------------------------------*/
  34 #define CFG_SYS_CLK                     80000000      /* 8MHz * 8 */
  35
  36 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  37
  38 #define CFG_SYS_MFD             0x02    /* PLL Multiplication Factor Devider */
  39 #define CFG_SYS_RFD             0x00    /* PLL Reduce Frecuency Devider */
  40
  41 /*----------------------------------------------------------------------*
  42  * Network                                                              *
  43  *----------------------------------------------------------------------*/
  44
  45 /*-------------------------------------------------------------------------
  46  * Low Level Configuration Settings
  47  * (address mappings, register initial values, etc.)
  48  * You should know what you are doing if you make changes here.
  49  *-----------------------------------------------------------------------*/
  50
  51 #define CFG_SYS_MBAR                    0x40000000
  52
  53 /*-----------------------------------------------------------------------
  54  * Definitions for initial stack pointer and data area (in DPRAM)
  55  *-----------------------------------------------------------------------*/
  56
  57 #define CFG_SYS_INIT_RAM_ADDR   0x20000000
  58 #define CFG_SYS_INIT_RAM_SIZE   0x10000
  59
  60 /*-----------------------------------------------------------------------
  61  * Start addresses for the final memory configuration
  62  * (Set up by the startup code)
  63  * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
  64  */
  65 #define CFG_SYS_SDRAM_BASE0             0x00000000
  66 #define CFG_SYS_SDRAM_SIZE0             16      /* SDRAM size in MB */
  67
  68 #define CFG_SYS_SDRAM_BASE              CFG_SYS_SDRAM_BASE0
  69 #define CFG_SYS_SDRAM_SIZE              CFG_SYS_SDRAM_SIZE0
  70
  71 /*
  72  * For booting Linux, the board info and command line data
  73  * have to be in the first 8 MB of memory, since this is
  74  * the maximum mapped by the Linux kernel during initialization ??
  75  */
  76 #define CFG_SYS_BOOTMAPSZ       (8 << 20) /* Initial Memory map for Linux */
  77
  78 /*-----------------------------------------------------------------------
  79  * FLASH organization
  80  */
  81
  82 #define CFG_SYS_FLASH_BASE              CFG_SYS_CS0_BASE
  83 #define CFG_SYS_INT_FLASH_BASE  0xF0000000
  84 #define CFG_SYS_INT_FLASH_ENABLE        0x21
  85
  86 #define CFG_SYS_FLASH_SIZE              16*1024*1024
  87
  88 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE }
  89
  90 /*-----------------------------------------------------------------------
  91  * Cache Configuration
  92  */
  93
  94 #define ICACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  95                                          CFG_SYS_INIT_RAM_SIZE - 8)
  96 #define DCACHE_STATUS                   (CFG_SYS_INIT_RAM_ADDR + \
  97                                          CFG_SYS_INIT_RAM_SIZE - 4)
  98 #define CFG_SYS_ICACHE_INV              (CF_CACR_CINV + CF_CACR_DCM)
  99 #define CFG_SYS_CACHE_ACR0              (CFG_SYS_SDRAM_BASE | \
 100                                          CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 101                                          CF_ACR_EN | CF_ACR_SM_ALL)
 102 #define CFG_SYS_CACHE_ICACR             (CF_CACR_CENB | CF_CACR_DISD | \
 103                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 104                                          CF_CACR_EUSP)
 105
 106 /*-----------------------------------------------------------------------
 107  * Memory bank definitions
 108  */
 109
 110 #define CFG_SYS_CS0_BASE                0xFF000000
 111 #define CFG_SYS_CS0_CTRL                0x00001980
 112 #define CFG_SYS_CS0_MASK                0x00FF0001
 113
 114 #define CFG_SYS_CS2_BASE                0xE0000000
 115 #define CFG_SYS_CS2_CTRL                0x00001980
 116 #define CFG_SYS_CS2_MASK                0x000F0001
 117
 118 #define CFG_SYS_CS3_BASE                0xE0100000
 119 #define CFG_SYS_CS3_CTRL                0x00001980
 120 #define CFG_SYS_CS3_MASK                0x000F0001
 121
 122 /*-----------------------------------------------------------------------
 123  * Port configuration
 124  */
 125 #define CFG_SYS_PACNT           0x0000000       /* Port A D[31:24] */
 126 #define CFG_SYS_PADDR           0x0000000
 127 #define CFG_SYS_PADAT           0x0000000
 128
 129 #define CFG_SYS_PBCNT           0x0000000       /* Port B D[23:16] */
 130 #define CFG_SYS_PBDDR           0x0000000
 131 #define CFG_SYS_PBDAT           0x0000000
 132
 133 #define CFG_SYS_PDCNT           0x0000000       /* Port D D[07:00] */
 134
 135 #define CFG_SYS_PASPAR          0x0F0F
 136 #define CFG_SYS_PEHLPAR         0xC0
 137 #define CFG_SYS_PUAPAR          0x0F
 138 #define CFG_SYS_DDRUA           0x05
 139 #define CFG_SYS_PJPAR           0xFF
 140
 141
 142 #endif  /* _CONFIG_M5282EVB_H */
 143 /*---------------------------------------------------------------------*/