include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  12
  13 /*----------------------------------------------------------------------*
  14  * High Level Configuration Options (easy to change)                    *
  15  *----------------------------------------------------------------------*/
  16
  17 #define CONFIG_SYS_UART_PORT            (0)
  18
  19 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  20
  21 #define CONFIG_BOOTCOMMAND "printenv"
  22
  23 /*----------------------------------------------------------------------*
  24  * Options                                                              *
  25  *----------------------------------------------------------------------*/
  26
  27 #define CONFIG_BOOT_RETRY_TIME  -1
  28 #define CONFIG_RESET_TO_RETRY
  29
  30 #define CONFIG_HW_WATCHDOG
  31
  32 #define STATUS_LED_ACTIVE               0
  33
  34 /*----------------------------------------------------------------------*
  35  * Configuration for environment                                        *
  36  * Environment is in the second sector of the first 256k of flash       *
  37  *----------------------------------------------------------------------*/
  38
  39 /*
  40  * BOOTP options
  41  */
  42 #define CONFIG_BOOTP_BOOTFILESIZE
  43
  44 #define CONFIG_MCFTMR
  45
  46 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  47 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  48
  49 /*#define CONFIG_SYS_DRAM_TEST          1 */
  50 #undef CONFIG_SYS_DRAM_TEST
  51
  52 /*----------------------------------------------------------------------*
  53  * Clock and PLL Configuration                                          *
  54  *----------------------------------------------------------------------*/
  55 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  56
  57 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  58
  59 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  60 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  61
  62 /*----------------------------------------------------------------------*
  63  * Network                                                              *
  64  *----------------------------------------------------------------------*/
  65
  66 #ifdef CONFIG_MCFFEC
  67 #define CONFIG_MII_INIT                 1
  68 #define CONFIG_SYS_DISCOVER_PHY
  69 #define CONFIG_SYS_RX_ETH_BUFFER        8
  70 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  71 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  72 #endif
  73
  74 /*-------------------------------------------------------------------------
  75  * Low Level Configuration Settings
  76  * (address mappings, register initial values, etc.)
  77  * You should know what you are doing if you make changes here.
  78  *-----------------------------------------------------------------------*/
  79
  80 #define CONFIG_SYS_MBAR                 0x40000000
  81
  82 /*-----------------------------------------------------------------------
  83  * Definitions for initial stack pointer and data area (in DPRAM)
  84  *-----------------------------------------------------------------------*/
  85
  86 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  87 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  88 #define CONFIG_SYS_GBL_DATA_OFFSET      \
  89         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  90 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  91
  92 /*-----------------------------------------------------------------------
  93  * Start addresses for the final memory configuration
  94  * (Set up by the startup code)
  95  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  96  */
  97 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
  98 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
  99
 100 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
 101 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
 102
 103 #define CONFIG_SYS_MONITOR_LEN          0x20000
 104 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 105
 106 /*
 107  * For booting Linux, the board info and command line data
 108  * have to be in the first 8 MB of memory, since this is
 109  * the maximum mapped by the Linux kernel during initialization ??
 110  */
 111 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 112
 113 /*-----------------------------------------------------------------------
 114  * FLASH organization
 115  */
 116 #define CONFIG_FLASH_SHOW_PROGRESS      45
 117
 118 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 119 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 120 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 121
 122 #define CONFIG_SYS_MAX_FLASH_SECT       128
 123 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 124 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 125
 126 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 127 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 128
 129 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 130
 131 /*-----------------------------------------------------------------------
 132  * Cache Configuration
 133  */
 134
 135 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 136                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 137 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 138                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 139 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 140 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 141                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 142                                          CF_ACR_EN | CF_ACR_SM_ALL)
 143 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 144                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 145                                          CF_CACR_EUSP)
 146
 147 /*-----------------------------------------------------------------------
 148  * Memory bank definitions
 149  */
 150
 151 #define CONFIG_SYS_CS0_BASE             0xFF000000
 152 #define CONFIG_SYS_CS0_CTRL             0x00001980
 153 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 154
 155 #define CONFIG_SYS_CS2_BASE             0xE0000000
 156 #define CONFIG_SYS_CS2_CTRL             0x00001980
 157 #define CONFIG_SYS_CS2_MASK             0x000F0001
 158
 159 #define CONFIG_SYS_CS3_BASE             0xE0100000
 160 #define CONFIG_SYS_CS3_CTRL             0x00001980
 161 #define CONFIG_SYS_CS3_MASK             0x000F0001
 162
 163 /*-----------------------------------------------------------------------
 164  * Port configuration
 165  */
 166 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 167 #define CONFIG_SYS_PADDR                0x0000000
 168 #define CONFIG_SYS_PADAT                0x0000000
 169
 170 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 171 #define CONFIG_SYS_PBDDR                0x0000000
 172 #define CONFIG_SYS_PBDAT                0x0000000
 173
 174 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 175 #define CONFIG_SYS_PCDDR                0x0000000
 176 #define CONFIG_SYS_PCDAT                0x0000000
 177
 178 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 179 #define CONFIG_SYS_PCDDR                0x0000000
 180 #define CONFIG_SYS_PCDAT                0x0000000
 181
 182 #define CONFIG_SYS_PASPAR               0x0F0F
 183 #define CONFIG_SYS_PEHLPAR              0xC0
 184 #define CONFIG_SYS_PUAPAR               0x0F
 185 #define CONFIG_SYS_DDRUA                0x05
 186 #define CONFIG_SYS_PJPAR                0xFF
 187
 188 /*-----------------------------------------------------------------------
 189  * I2C
 190  */
 191
 192 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 193
 194 #ifdef CONFIG_CMD_DATE
 195 #define CONFIG_RTC_DS1338
 196 #define CONFIG_I2C_RTC_ADDR             0x68
 197 #endif
 198
 199 /*-----------------------------------------------------------------------
 200  * VIDEO configuration
 201  */
 202
 203 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 204 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 205 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 206
 207 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 208 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 209 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 210
 211 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 212 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 213 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 214
 215 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 216 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 217 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 218
 219 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 220 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 221 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 222
 223 #endif  /* _CONFIG_M5282EVB_H */
 224 /*---------------------------------------------------------------------*/