include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  12
  13 /*----------------------------------------------------------------------*
  14  * High Level Configuration Options (easy to change)                    *
  15  *----------------------------------------------------------------------*/
  16
  17 #define CONFIG_SYS_UART_PORT            (0)
  18
  19 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  20
  21 /*----------------------------------------------------------------------*
  22  * Options                                                              *
  23  *----------------------------------------------------------------------*/
  24
  25 #define CONFIG_BOOT_RETRY_TIME  -1
  26 #define CONFIG_RESET_TO_RETRY
  27
  28 #define CONFIG_HW_WATCHDOG
  29
  30 #define STATUS_LED_ACTIVE               0
  31
  32 /*----------------------------------------------------------------------*
  33  * Configuration for environment                                        *
  34  * Environment is in the second sector of the first 256k of flash       *
  35  *----------------------------------------------------------------------*/
  36
  37 /*
  38  * BOOTP options
  39  */
  40 #define CONFIG_BOOTP_BOOTFILESIZE
  41
  42 #define CONFIG_MCFTMR
  43
  44 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  45 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  46
  47 /*#define CONFIG_SYS_DRAM_TEST          1 */
  48 #undef CONFIG_SYS_DRAM_TEST
  49
  50 /*----------------------------------------------------------------------*
  51  * Clock and PLL Configuration                                          *
  52  *----------------------------------------------------------------------*/
  53 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  54
  55 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  56
  57 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  58 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  59
  60 /*----------------------------------------------------------------------*
  61  * Network                                                              *
  62  *----------------------------------------------------------------------*/
  63
  64 #ifdef CONFIG_MCFFEC
  65 #define CONFIG_MII_INIT                 1
  66 #define CONFIG_SYS_DISCOVER_PHY
  67 #define CONFIG_SYS_RX_ETH_BUFFER        8
  68 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  69 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  70 #endif
  71
  72 /*-------------------------------------------------------------------------
  73  * Low Level Configuration Settings
  74  * (address mappings, register initial values, etc.)
  75  * You should know what you are doing if you make changes here.
  76  *-----------------------------------------------------------------------*/
  77
  78 #define CONFIG_SYS_MBAR                 0x40000000
  79
  80 /*-----------------------------------------------------------------------
  81  * Definitions for initial stack pointer and data area (in DPRAM)
  82  *-----------------------------------------------------------------------*/
  83
  84 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  85 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  86 #define CONFIG_SYS_GBL_DATA_OFFSET      \
  87         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  88 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  89
  90 /*-----------------------------------------------------------------------
  91  * Start addresses for the final memory configuration
  92  * (Set up by the startup code)
  93  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  94  */
  95 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
  96 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
  97
  98 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
  99 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
 100
 101 #define CONFIG_SYS_MONITOR_LEN          0x20000
 102 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 103
 104 /*
 105  * For booting Linux, the board info and command line data
 106  * have to be in the first 8 MB of memory, since this is
 107  * the maximum mapped by the Linux kernel during initialization ??
 108  */
 109 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 110
 111 /*-----------------------------------------------------------------------
 112  * FLASH organization
 113  */
 114 #define CONFIG_FLASH_SHOW_PROGRESS      45
 115
 116 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 117 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 118 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 119
 120 #define CONFIG_SYS_MAX_FLASH_SECT       128
 121 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 122 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 123
 124 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 125 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 126
 127 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 128
 129 /*-----------------------------------------------------------------------
 130  * Cache Configuration
 131  */
 132
 133 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 134                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 135 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 136                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 137 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 138 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 139                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 140                                          CF_ACR_EN | CF_ACR_SM_ALL)
 141 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 142                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 143                                          CF_CACR_EUSP)
 144
 145 /*-----------------------------------------------------------------------
 146  * Memory bank definitions
 147  */
 148
 149 #define CONFIG_SYS_CS0_BASE             0xFF000000
 150 #define CONFIG_SYS_CS0_CTRL             0x00001980
 151 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 152
 153 #define CONFIG_SYS_CS2_BASE             0xE0000000
 154 #define CONFIG_SYS_CS2_CTRL             0x00001980
 155 #define CONFIG_SYS_CS2_MASK             0x000F0001
 156
 157 #define CONFIG_SYS_CS3_BASE             0xE0100000
 158 #define CONFIG_SYS_CS3_CTRL             0x00001980
 159 #define CONFIG_SYS_CS3_MASK             0x000F0001
 160
 161 /*-----------------------------------------------------------------------
 162  * Port configuration
 163  */
 164 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 165 #define CONFIG_SYS_PADDR                0x0000000
 166 #define CONFIG_SYS_PADAT                0x0000000
 167
 168 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 169 #define CONFIG_SYS_PBDDR                0x0000000
 170 #define CONFIG_SYS_PBDAT                0x0000000
 171
 172 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 173 #define CONFIG_SYS_PCDDR                0x0000000
 174 #define CONFIG_SYS_PCDAT                0x0000000
 175
 176 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 177 #define CONFIG_SYS_PCDDR                0x0000000
 178 #define CONFIG_SYS_PCDAT                0x0000000
 179
 180 #define CONFIG_SYS_PASPAR               0x0F0F
 181 #define CONFIG_SYS_PEHLPAR              0xC0
 182 #define CONFIG_SYS_PUAPAR               0x0F
 183 #define CONFIG_SYS_DDRUA                0x05
 184 #define CONFIG_SYS_PJPAR                0xFF
 185
 186 /*-----------------------------------------------------------------------
 187  * I2C
 188  */
 189
 190 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 191
 192 #ifdef CONFIG_CMD_DATE
 193 #define CONFIG_RTC_DS1338
 194 #define CONFIG_I2C_RTC_ADDR             0x68
 195 #endif
 196
 197 /*-----------------------------------------------------------------------
 198  * VIDEO configuration
 199  */
 200
 201 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 202 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 203 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 204
 205 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 206 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 207 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 208
 209 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 210 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 211 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 212
 213 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 214 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 215 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 216
 217 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 218 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 219 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 220
 221 #endif  /* _CONFIG_M5282EVB_H */
 222 /*---------------------------------------------------------------------*/