1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
5 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
8 #ifndef _CONFIG_EB_CPU5282_H_
9 #define _CONFIG_EB_CPU5282_H_
11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
13 /*----------------------------------------------------------------------*
14 * High Level Configuration Options (easy to change) *
15 *----------------------------------------------------------------------*/
17 #define CONFIG_SYS_UART_PORT (0)
19 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
21 /*----------------------------------------------------------------------*
23 *----------------------------------------------------------------------*/
25 #define STATUS_LED_ACTIVE 0
27 /*----------------------------------------------------------------------*
28 * Configuration for environment *
29 * Environment is in the second sector of the first 256k of flash *
30 *----------------------------------------------------------------------*/
32 /*#define CONFIG_SYS_DRAM_TEST 1 */
33 #undef CONFIG_SYS_DRAM_TEST
35 /*----------------------------------------------------------------------*
36 * Clock and PLL Configuration *
37 *----------------------------------------------------------------------*/
38 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
40 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
42 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
43 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
45 /*----------------------------------------------------------------------*
47 *----------------------------------------------------------------------*/
50 #define CONFIG_SYS_DISCOVER_PHY
51 #define CONFIG_OVERWRITE_ETHADDR_ONCE
54 /*-------------------------------------------------------------------------
55 * Low Level Configuration Settings
56 * (address mappings, register initial values, etc.)
57 * You should know what you are doing if you make changes here.
58 *-----------------------------------------------------------------------*/
60 #define CONFIG_SYS_MBAR 0x40000000
62 /*-----------------------------------------------------------------------
63 * Definitions for initial stack pointer and data area (in DPRAM)
64 *-----------------------------------------------------------------------*/
66 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
67 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
68 #define CONFIG_SYS_GBL_DATA_OFFSET \
69 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
70 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
72 /*-----------------------------------------------------------------------
73 * Start addresses for the final memory configuration
74 * (Set up by the startup code)
75 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
77 #define CONFIG_SYS_SDRAM_BASE0 0x00000000
78 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
81 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
83 #define CONFIG_SYS_MONITOR_LEN 0x20000
86 * For booting Linux, the board info and command line data
87 * have to be in the first 8 MB of memory, since this is
88 * the maximum mapped by the Linux kernel during initialization ??
90 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
92 /*-----------------------------------------------------------------------
95 #define CONFIG_FLASH_SHOW_PROGRESS 45
97 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
98 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
99 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
101 #define CONFIG_SYS_MAX_FLASH_SECT 128
102 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
104 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024
105 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
107 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
109 /*-----------------------------------------------------------------------
110 * Cache Configuration
113 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
114 CONFIG_SYS_INIT_RAM_SIZE - 8)
115 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
116 CONFIG_SYS_INIT_RAM_SIZE - 4)
117 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
118 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
119 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
120 CF_ACR_EN | CF_ACR_SM_ALL)
121 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
122 CF_CACR_CEIB | CF_CACR_DBWE | \
125 /*-----------------------------------------------------------------------
126 * Memory bank definitions
129 #define CONFIG_SYS_CS0_BASE 0xFF000000
130 #define CONFIG_SYS_CS0_CTRL 0x00001980
131 #define CONFIG_SYS_CS0_MASK 0x00FF0001
133 #define CONFIG_SYS_CS2_BASE 0xE0000000
134 #define CONFIG_SYS_CS2_CTRL 0x00001980
135 #define CONFIG_SYS_CS2_MASK 0x000F0001
137 #define CONFIG_SYS_CS3_BASE 0xE0100000
138 #define CONFIG_SYS_CS3_CTRL 0x00001980
139 #define CONFIG_SYS_CS3_MASK 0x000F0001
141 /*-----------------------------------------------------------------------
144 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
145 #define CONFIG_SYS_PADDR 0x0000000
146 #define CONFIG_SYS_PADAT 0x0000000
148 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
149 #define CONFIG_SYS_PBDDR 0x0000000
150 #define CONFIG_SYS_PBDAT 0x0000000
152 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
153 #define CONFIG_SYS_PCDDR 0x0000000
154 #define CONFIG_SYS_PCDAT 0x0000000
156 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
157 #define CONFIG_SYS_PCDDR 0x0000000
158 #define CONFIG_SYS_PCDAT 0x0000000
160 #define CONFIG_SYS_PASPAR 0x0F0F
161 #define CONFIG_SYS_PEHLPAR 0xC0
162 #define CONFIG_SYS_PUAPAR 0x0F
163 #define CONFIG_SYS_DDRUA 0x05
164 #define CONFIG_SYS_PJPAR 0xFF
166 /*-----------------------------------------------------------------------
170 #ifdef CONFIG_CMD_DATE
171 #define CONFIG_RTC_DS1338
172 #define CONFIG_I2C_RTC_ADDR 0x68
175 /*-----------------------------------------------------------------------
176 * VIDEO configuration
179 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
180 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
181 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
183 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
184 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
185 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
187 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
188 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
189 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
191 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
192 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
193 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
195 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
196 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
197 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
199 #endif /* _CONFIG_M5282EVB_H */
200 /*---------------------------------------------------------------------*/