include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  12
  13 /*----------------------------------------------------------------------*
  14  * High Level Configuration Options (easy to change)                    *
  15  *----------------------------------------------------------------------*/
  16
  17 #define CONFIG_SYS_UART_PORT            (0)
  18
  19 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  20
  21 /*----------------------------------------------------------------------*
  22  * Options                                                              *
  23  *----------------------------------------------------------------------*/
  24
  25 #define CONFIG_BOOT_RETRY_TIME  -1
  26 #define CONFIG_RESET_TO_RETRY
  27
  28 #define STATUS_LED_ACTIVE               0
  29
  30 /*----------------------------------------------------------------------*
  31  * Configuration for environment                                        *
  32  * Environment is in the second sector of the first 256k of flash       *
  33  *----------------------------------------------------------------------*/
  34
  35 /*
  36  * BOOTP options
  37  */
  38 #define CONFIG_BOOTP_BOOTFILESIZE
  39
  40 #define CONFIG_MCFTMR
  41
  42 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  43 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  44
  45 /*#define CONFIG_SYS_DRAM_TEST          1 */
  46 #undef CONFIG_SYS_DRAM_TEST
  47
  48 /*----------------------------------------------------------------------*
  49  * Clock and PLL Configuration                                          *
  50  *----------------------------------------------------------------------*/
  51 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  52
  53 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  54
  55 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  56 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  57
  58 /*----------------------------------------------------------------------*
  59  * Network                                                              *
  60  *----------------------------------------------------------------------*/
  61
  62 #ifdef CONFIG_MCFFEC
  63 #define CONFIG_MII_INIT                 1
  64 #define CONFIG_SYS_DISCOVER_PHY
  65 #define CONFIG_SYS_RX_ETH_BUFFER        8
  66 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  67 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  68 #endif
  69
  70 /*-------------------------------------------------------------------------
  71  * Low Level Configuration Settings
  72  * (address mappings, register initial values, etc.)
  73  * You should know what you are doing if you make changes here.
  74  *-----------------------------------------------------------------------*/
  75
  76 #define CONFIG_SYS_MBAR                 0x40000000
  77
  78 /*-----------------------------------------------------------------------
  79  * Definitions for initial stack pointer and data area (in DPRAM)
  80  *-----------------------------------------------------------------------*/
  81
  82 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  83 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  84 #define CONFIG_SYS_GBL_DATA_OFFSET      \
  85         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  86 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  87
  88 /*-----------------------------------------------------------------------
  89  * Start addresses for the final memory configuration
  90  * (Set up by the startup code)
  91  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  92  */
  93 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
  94 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
  95
  96 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
  97 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
  98
  99 #define CONFIG_SYS_MONITOR_LEN          0x20000
 100 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 101
 102 /*
 103  * For booting Linux, the board info and command line data
 104  * have to be in the first 8 MB of memory, since this is
 105  * the maximum mapped by the Linux kernel during initialization ??
 106  */
 107 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 108
 109 /*-----------------------------------------------------------------------
 110  * FLASH organization
 111  */
 112 #define CONFIG_FLASH_SHOW_PROGRESS      45
 113
 114 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 115 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 116 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 117
 118 #define CONFIG_SYS_MAX_FLASH_SECT       128
 119 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 120 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 121
 122 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 123 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 124
 125 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 126
 127 /*-----------------------------------------------------------------------
 128  * Cache Configuration
 129  */
 130
 131 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 132                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 133 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 134                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 135 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 136 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 137                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 138                                          CF_ACR_EN | CF_ACR_SM_ALL)
 139 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 140                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 141                                          CF_CACR_EUSP)
 142
 143 /*-----------------------------------------------------------------------
 144  * Memory bank definitions
 145  */
 146
 147 #define CONFIG_SYS_CS0_BASE             0xFF000000
 148 #define CONFIG_SYS_CS0_CTRL             0x00001980
 149 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 150
 151 #define CONFIG_SYS_CS2_BASE             0xE0000000
 152 #define CONFIG_SYS_CS2_CTRL             0x00001980
 153 #define CONFIG_SYS_CS2_MASK             0x000F0001
 154
 155 #define CONFIG_SYS_CS3_BASE             0xE0100000
 156 #define CONFIG_SYS_CS3_CTRL             0x00001980
 157 #define CONFIG_SYS_CS3_MASK             0x000F0001
 158
 159 /*-----------------------------------------------------------------------
 160  * Port configuration
 161  */
 162 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 163 #define CONFIG_SYS_PADDR                0x0000000
 164 #define CONFIG_SYS_PADAT                0x0000000
 165
 166 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 167 #define CONFIG_SYS_PBDDR                0x0000000
 168 #define CONFIG_SYS_PBDAT                0x0000000
 169
 170 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 171 #define CONFIG_SYS_PCDDR                0x0000000
 172 #define CONFIG_SYS_PCDAT                0x0000000
 173
 174 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 175 #define CONFIG_SYS_PCDDR                0x0000000
 176 #define CONFIG_SYS_PCDAT                0x0000000
 177
 178 #define CONFIG_SYS_PASPAR               0x0F0F
 179 #define CONFIG_SYS_PEHLPAR              0xC0
 180 #define CONFIG_SYS_PUAPAR               0x0F
 181 #define CONFIG_SYS_DDRUA                0x05
 182 #define CONFIG_SYS_PJPAR                0xFF
 183
 184 /*-----------------------------------------------------------------------
 185  * I2C
 186  */
 187
 188 #ifdef CONFIG_CMD_DATE
 189 #define CONFIG_RTC_DS1338
 190 #define CONFIG_I2C_RTC_ADDR             0x68
 191 #endif
 192
 193 /*-----------------------------------------------------------------------
 194  * VIDEO configuration
 195  */
 196
 197 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 198 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 199 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 200
 201 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 202 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 203 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 204
 205 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 206 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 207 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 208
 209 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 210 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 211 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 212
 213 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 214 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 215 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 216
 217 #endif  /* _CONFIG_M5282EVB_H */
 218 /*---------------------------------------------------------------------*/