include/configs/digsy_mtc.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2005-2007
   6  * Modified for InterControl digsyMTC MPC5200 board by
   7  * Frank Bodammer, GCD Hard- & Software GmbH,
   8  *                 frank.bodammer@gcd-solutions.de
   9  *
  10  * (C) Copyright 2009 Semihalf
  11  * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  24 #define CONFIG_DIGSY_MTC        1       /* ... on InterControl digsyMTC board */
  25
  26 /*
  27  * Valid values for CONFIG_SYS_TEXT_BASE are:
  28  * 0xFFF00000   boot high (standard configuration)
  29  * 0xFE000000   boot low
  30  * 0x00100000   boot from RAM (for testing only)
  31  */
  32 #ifndef CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
  34 #endif
  35
  36 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  37
  38 #define CONFIG_SYS_CACHELINE_SIZE       32
  39
  40 /*
  41  * Serial console configuration
  42  */
  43 #define CONFIG_PSC_CONSOLE      4       /* console is on PSC4  */
  44 #define CONFIG_SYS_BAUDRATE_TABLE       \
  45         { 9600, 19200, 38400, 57600, 115200, 230400 }
  46
  47 /*
  48  * PCI Mapping:
  49  * 0x40000000 - 0x4fffffff - PCI Memory
  50  * 0x50000000 - 0x50ffffff - PCI IO Space
  51  */
  52 #define CONFIG_PCI_SCAN_SHOW    1
  53 #define CONFIG_PCI_BOOTDELAY    250
  54
  55 #define CONFIG_PCI_MEM_BUS      0x40000000
  56 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  57 #define CONFIG_PCI_MEM_SIZE     0x10000000
  58
  59 #define CONFIG_PCI_IO_BUS       0x50000000
  60 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  61 #define CONFIG_PCI_IO_SIZE      0x01000000
  62
  63 #define CONFIG_BZIP2
  64
  65 /*
  66  * Video
  67  */
  68
  69 #ifdef CONFIG_VIDEO
  70 #define CONFIG_VIDEO_MB862xx
  71 #define CONFIG_VIDEO_MB862xx_ACCEL
  72 #define CONFIG_VIDEO_CORALP
  73 #define CONFIG_VIDEO_LOGO
  74 #define CONFIG_VIDEO_BMP_LOGO
  75 #define CONFIG_SPLASH_SCREEN
  76 #define CONFIG_VIDEO_BMP_GZIP
  77 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
  78
  79 /* Coral-PA clock frequency, geo and other both 133MHz */
  80 #define CONFIG_SYS_MB862xx_CCF  0x00050000
  81 /* Video SDRAM parameters */
  82 #define CONFIG_SYS_MB862xx_MMR  0x11d7fa72
  83 #endif
  84
  85 /*
  86  * Command line configuration.
  87  */
  88 #define CONFIG_CMD_DATE
  89 #define CONFIG_CMD_DIAG
  90 #define CONFIG_CMD_EEPROM
  91 #define CONFIG_CMD_IDE
  92 #define CONFIG_CMD_IRQ
  93 #define CONFIG_CMD_PCI
  94 #define CONFIG_CMD_REGINFO
  95 #define CONFIG_CMD_SAVES
  96
  97 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
  98 #define CONFIG_SYS_LOWBOOT      1
  99 #endif
 100
 101 /*
 102  * Autobooting
 103  */
 104
 105 #undef  CONFIG_BOOTARGS
 106
 107 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 108         "fw_image=digsyMPC.img\0"                                       \
 109         "mtcb_start=mtc led diag orange; run mtcb_1\0"                  \
 110         "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "           \
 111                 "do mtc led $x; done\0"                                 \
 112         "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "       \
 113                 "else run mtcb_fw; fi\0"                                \
 114         "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "           \
 115                 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"   \
 116         "mtcb_update=mtc led user1 orange;"                             \
 117                 "while mtc key; do ; done; run mtcb_2;\0"               \
 118         "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"     \
 119         "mtcb_usb1=if fatload usb 0 400000 script.img; "                \
 120                 "then run mtcb_doscript; else run mtcb_usb2; fi\0"      \
 121         "mtcb_usb2=if fatload usb 0 400000 $fw_image; "                 \
 122                 "then run mtcb_dousb; else run mtcb_ide; fi\0"          \
 123         "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "      \
 124                 "run mtcb_wait_flickr mtcb_ds_1;\0"                     \
 125         "mtcb_ds_1=if imi 400000; then mtc led usbbusy; "               \
 126                 "source 400000; else run mtcb_error; fi\0"              \
 127         "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"     \
 128         "mtcb_du_1=if imi 400000; then run mtcb_du_2; "                 \
 129                 "else run mtcb_error; fi\0"                             \
 130         "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "         \
 131                 "run mtcb_checkfw\0"                                    \
 132         "mtcb_checkfw=if imi ff000000; then run mtcb_success; "         \
 133                 "else run mtcb_error; fi\0"                             \
 134         "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
 135         "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"            \
 136         "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
 137         "mtcb_uledflckr=mtc led user1 orange 11\0"                      \
 138         "mtcb_error=mtc led user1 red\0"                                \
 139         "mtcb_clear=erase ff000000 ff0fffff\0"                          \
 140         "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"                  \
 141         "mtcb_success=mtc led user1 green\0"                            \
 142         "mtcb_ide=if fatload ide 0 400000 $fw_image;"                   \
 143                 "then run mtcb_doide; else run mtcb_error; fi\0"        \
 144         "mtcb_doide=mtc led user2 green 1;"                             \
 145                 "run mtcb_wait_flickr mtcb_di_1;\0"                     \
 146         "mtcb_di_1=if imi 400000; then run mtcb_di_2;"                  \
 147                 "else run mtcb_error; fi\0"                             \
 148         "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"        \
 149         "ramdisk_num_sector=16\0"                                       \
 150         "flash_base=ff000000\0"                                         \
 151         "flashdisk_size=e00000\0"                                       \
 152         "env_sector=fff60000\0"                                         \
 153         "flashdisk_start=ff100000\0"                                    \
 154         "load_cmd=tftp 400000 digsyMPC.img\0"                           \
 155         "clear_cmd=erase ff000000 ff0fffff\0"                           \
 156         "flash_cmd=cp.b 400000 ff000000 ${filesize}\0"                  \
 157         "update_cmd=run load_cmd; "                                     \
 158         "iminfo 400000; "                                               \
 159         "run clear_cmd flash_cmd; "                                     \
 160         "iminfo ff000000\0"                                             \
 161         "spi_driver=yes\0"                                              \
 162         "spi_watchdog=no\0"                                             \
 163         "ftps_start=yes\0"                                              \
 164         "ftps_user1=admin\0"                                            \
 165         "ftps_pass1=admin\0"                                            \
 166         "ftps_base1=/\0"                                                \
 167         "ftps_home1=/\0"                                                \
 168         "plc_sio_srv=no\0"                                              \
 169         "plc_sio_baud=57600\0"                                          \
 170         "plc_sio_parity=no\0"                                           \
 171         "plc_sio_stop=1\0"                                              \
 172         "plc_sio_com=2\0"                                               \
 173         "plc_eth_srv=yes\0"                                             \
 174         "plc_eth_port=1200\0"                                           \
 175         "plc_root=/ide/\0"                                              \
 176         "diag_level=0\0"                                                \
 177         "webvisu=no\0"                                                  \
 178         "plc_can1_routing=no\0"                                         \
 179         "plc_can1_baudrate=250\0"                                       \
 180         "plc_can2_routing=no\0"                                         \
 181         "plc_can2_baudrate=250\0"                                       \
 182         "plc_can3_routing=no\0"                                         \
 183         "plc_can3_baudrate=250\0"                                       \
 184         "plc_can4_routing=no\0"                                         \
 185         "plc_can4_baudrate=250\0"                                       \
 186         "netdev=eth0\0"                                                 \
 187         "console=ttyPSC0\0"                                             \
 188         "kernel_addr_r=400000\0"                                        \
 189         "fdt_addr_r=600000\0"                                           \
 190         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 191         "nfsroot=${serverip}:${rootpath}\0"                             \
 192         "addip=setenv bootargs ${bootargs} "                            \
 193         "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
 194         "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
 195         "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
 196         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 197         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 198                 "tftp ${fdt_addr_r} ${fdt_file};"                       \
 199                 "run nfsargs addip addcons;"                            \
 200                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 201         "load=tftp 200000 ${u-boot}\0"                                  \
 202         "update=protect off FFF00000 +${filesize};"                     \
 203                 "erase FFF00000 +${filesize};"                          \
 204                 "cp.b 200000 FFF00000 ${filesize};"                     \
 205                 "protect on FFF00000 +${filesize}\0"                    \
 206         ""
 207
 208 #define CONFIG_BOOTCOMMAND      "run mtcb_start"
 209
 210 /*
 211  * I2C configuration
 212  */
 213 #define CONFIG_HARD_I2C         1
 214 #define CONFIG_SYS_I2C_MODULE   1
 215 #define CONFIG_SYS_I2C_SPEED    100000
 216 #define CONFIG_SYS_I2C_SLAVE    0x7F
 217
 218 /*
 219  * EEPROM configuration
 220  */
 221 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 222 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 225
 226 /*
 227  * RTC configuration
 228  */
 229 #if defined(CONFIG_DIGSY_REV5)
 230 #define CONFIG_SYS_I2C_RTC_ADDR 0x56
 231 #define CONFIG_RTC_RV3029
 232 /* Enable 5k Ohm trickle charge resistor */
 233 #define CONFIG_SYS_RV3029_TCR   0x20
 234 #else
 235 #define CONFIG_RTC_DS1337
 236 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 237 #define CONFIG_SYS_DS1339_TCR_VAL       0xAB    /* diode + 4k resistor */
 238 #endif
 239
 240 /*
 241  * Flash configuration
 242  */
 243 #define CONFIG_SYS_FLASH_CFI            1
 244 #define CONFIG_FLASH_CFI_DRIVER 1
 245
 246 #if defined(CONFIG_DIGSY_REV5)
 247 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 248 #define CONFIG_SYS_FLASH_BASE_CS1       0xFC000000
 249 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 250 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
 251                                         CONFIG_SYS_FLASH_BASE_CS1}
 252 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 253 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 254 #else
 255 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 256 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 257 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 258 #endif
 259
 260 #define CONFIG_SYS_MAX_FLASH_SECT       256
 261 #define CONFIG_FLASH_16BIT
 262 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
 263 #define CONFIG_SYS_FLASH_SIZE   0x01000000
 264 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
 265 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 266
 267 #define OF_CPU                  "PowerPC,5200@0"
 268 #define OF_SOC                  "soc5200@f0000000"
 269 #define OF_TBCLK                (bd->bi_busfreq / 4)
 270
 271 #define CONFIG_BOARD_EARLY_INIT_R
 272 #define CONFIG_MISC_INIT_R
 273
 274 /*
 275  * Environment settings
 276  */
 277 #define CONFIG_ENV_IS_IN_FLASH  1
 278 #if defined(CONFIG_LOWBOOT)
 279 #define CONFIG_ENV_ADDR         0xFF060000
 280 #else   /* CONFIG_LOWBOOT */
 281 #define CONFIG_ENV_ADDR         0xFFF60000
 282 #endif  /* CONFIG_LOWBOOT */
 283 #define CONFIG_ENV_SIZE         0x10000
 284 #define CONFIG_ENV_SECT_SIZE    0x20000
 285 #define CONFIG_ENV_OVERWRITE    1
 286
 287 /*
 288  * Memory map
 289  */
 290 #define CONFIG_SYS_MBAR         0xF0000000
 291 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 292 #if !defined(CONFIG_SYS_LOWBOOT)
 293 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 294 #else
 295 #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
 296 #endif
 297
 298 /*
 299  *  Use SRAM until RAM will be available
 300  */
 301 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 302 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
 303
 304 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 305         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 306 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 307
 308 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 309 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 310 #define CONFIG_SYS_RAMBOOT              1
 311 #endif
 312
 313 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 314 #define CONFIG_SYS_MALLOC_LEN   (4096 << 10)
 315 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
 316
 317 /*
 318  * Ethernet configuration
 319  */
 320 #define CONFIG_MPC5xxx_FEC      1
 321 #define CONFIG_MPC5xxx_FEC_MII100
 322 #if defined(CONFIG_DIGSY_REV5)
 323 #define CONFIG_PHY_ADDR         0x01
 324 #else
 325 #define CONFIG_PHY_ADDR         0x00
 326 #endif
 327 #define CONFIG_PHY_RESET_DELAY  1000
 328
 329 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 330
 331 /*
 332  * GPIO configuration
 333  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
 334  *  Bit 0   (mask 0x80000000) : 0x1
 335  * SPI on Tmr2/3/4/5 pins
 336  *  Bit 2:3 (mask 0x30000000) : 0x2
 337  * ATA cs0/1 on csb_4/5
 338  *  Bit 6:7 (mask 0x03000000) : 0x2
 339  * Ethernet 100Mbit with MD
 340  *  Bits 12:15 (mask 0x000f0000): 0x5
 341  * USB - Two UARTs
 342  *  Bits 18:19 (mask 0x00003000) : 0x2
 343  * PSC3 - USB2 on PSC3
 344  *  Bits 20:23 (mask 0x00000f00) : 0x1
 345  * PSC2 - CAN1&2 on PSC2 pins
 346  *  Bits 25:27 (mask 0x00000070) : 0x1
 347  * PSC1 - AC97 functionality
 348  *  Bits 29:31 (mask 0x00000007) : 0x2
 349  */
 350 #define CONFIG_SYS_GPS_PORT_CONFIG      0xA2552112
 351
 352 /*
 353  * Miscellaneous configurable options
 354  */
 355 #define CONFIG_SYS_LONGHELP
 356 #define CONFIG_AUTO_COMPLETE    1
 357 #define CONFIG_CMDLINE_EDITING  1
 358
 359 #define CONFIG_MX_CYCLIC        1
 360
 361 #define CONFIG_SYS_CBSIZE               1024
 362 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 363 #define CONFIG_SYS_MAXARGS              32
 364 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 365
 366 #define CONFIG_SYS_ALT_MEMTEST
 367 #define CONFIG_SYS_MEMTEST_SCRATCH      0x00001000
 368 #define CONFIG_SYS_MEMTEST_START        0x00010000
 369 #define CONFIG_SYS_MEMTEST_END          0x019fffff
 370
 371 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 372
 373 /*
 374  * Various low-level settings
 375  */
 376 #define CONFIG_SYS_SDRAM_CS1            1
 377 #define CONFIG_SYS_XLB_PIPELINING       1
 378
 379 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 380 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 381
 382 #if defined(CONFIG_SYS_LOWBOOT)
 383 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 384 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 385 #define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 386 #endif
 387
 388 #define CONFIG_SYS_CS4_START            0x60000000
 389 #define CONFIG_SYS_CS4_SIZE             0x1000
 390 #define CONFIG_SYS_CS4_CFG              0x0008FC00
 391
 392 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 393 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 394 #define CONFIG_SYS_CS0_CFG              0x0002DD00
 395
 396 #if defined(CONFIG_DIGSY_REV5)
 397 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE_CS1
 398 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 399 #define CONFIG_SYS_CS1_CFG              0x0002DD00
 400 #endif
 401
 402 #define CONFIG_SYS_CS_BURST             0x00000000
 403 #define CONFIG_SYS_CS_DEADCYCLE 0x11111111
 404
 405 #if !defined(CONFIG_SYS_LOWBOOT)
 406 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 407 #else
 408 #define CONFIG_SYS_RESET_ADDRESS        0xff000100
 409 #endif
 410
 411 /*
 412  * USB
 413  */
 414 #define CONFIG_USB_OHCI_NEW
 415 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 416
 417 #define CONFIG_USB_CLOCK        0x00013333
 418 #define CONFIG_USB_CONFIG       0x00002000
 419
 420 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 421 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
 422 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
 423 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 424
 425 /*
 426  * IDE/ATA
 427  */
 428 #define CONFIG_IDE_RESET
 429 #define CONFIG_IDE_PREINIT
 430
 431 #define CONFIG_SYS_ATA_CS_ON_I2C2
 432 #define CONFIG_SYS_IDE_MAXBUS           1
 433 #define CONFIG_SYS_IDE_MAXDEVICE        1
 434
 435 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 436 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 437 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 438 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 439 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 440 #define CONFIG_SYS_ATA_STRIDE           4
 441
 442 #define CONFIG_ATAPI            1
 443 #define CONFIG_LBA48            1
 444
 445 #endif /* __CONFIG_H */