1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Embest/Timll DevKit3250 board configuration file
5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
8 #ifndef __CONFIG_DEVKIT3250_H__
9 #define __CONFIG_DEVKIT3250_H__
11 /* SoC and board defines */
12 #include <linux/sizes.h>
13 #include <asm/arch/cpu.h>
15 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
17 #if !defined(CONFIG_SPL_BUILD)
18 #define CONFIG_SKIP_LOWLEVEL_INIT
22 * Memory configurations
24 #define CONFIG_SYS_MALLOC_LEN SZ_1M
25 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
26 #define CONFIG_SYS_SDRAM_SIZE SZ_64M
28 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
30 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
31 - GENERATED_GBL_DATA_SIZE)
36 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
41 #if !defined(CONFIG_SPL_BUILD)
42 #define CONFIG_DMA_LPC32XX
48 #define CONFIG_SYS_I2C
49 #define CONFIG_SYS_I2C_LPC32XX
50 #define CONFIG_SYS_I2C_SPEED 100000
55 #define CONFIG_LPC32XX_GPIO
60 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
66 #define CONFIG_LPC32XX_ETH
67 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
72 #define CONFIG_SYS_MAX_FLASH_BANKS 1
73 #define CONFIG_SYS_MAX_FLASH_SECT 71
74 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
75 #define CONFIG_SYS_FLASH_SIZE SZ_4M
80 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
81 #define CONFIG_SYS_MAX_NAND_DEVICE 1
82 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
87 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
88 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
89 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
90 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
91 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
92 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
93 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
94 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
96 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
97 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
102 #define CONFIG_USB_OHCI_LPC32XX
103 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
106 * U-Boot General Configurations
108 #define CONFIG_SYS_CBSIZE 1024
109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
112 * Pass open firmware flat tree
119 #define CONFIG_BOOTCOMMAND \
121 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
122 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
123 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
124 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
125 "bootm ${loadaddr} - ${dtbaddr}"
127 #define CONFIG_EXTRA_ENV_SETTINGS \
129 "ethaddr=00:01:90:00:C0:81\0" \
130 "dtbaddr=0x81000000\0" \
131 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
132 "tftpdir=vladimir/oe/devkit3250\0" \
133 "userargs=oops=panic\0"
142 #define CONFIG_CMDLINE_TAG
143 #define CONFIG_SETUP_MEMORY_TAGS
145 #define CONFIG_BOOTFILE "uImage"
146 #define CONFIG_LOADADDR 0x80008000
149 * SPL specific defines
151 /* SPL will be executed at offset 0 */
153 /* SPL will use SRAM as stack */
154 #define CONFIG_SPL_STACK 0x0000FFF8
156 /* Use the framework and generic lib */
158 /* SPL will use serial */
160 /* SPL loads an image from NAND */
161 #define CONFIG_SPL_NAND_RAW_ONLY
162 #define CONFIG_SPL_NAND_DRIVERS
164 #define CONFIG_SPL_NAND_ECC
165 #define CONFIG_SPL_NAND_SOFTECC
167 #define CONFIG_SPL_MAX_SIZE 0x20000
168 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
170 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
171 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
172 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
174 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
175 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
177 /* See common/spl/spl.c spl_set_header_raw_uboot() */
178 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
181 * Include SoC specific configuration
183 #include <asm/arch/config.h>
185 #endif /* __CONFIG_DEVKIT3250_H__*/