include/configs/devkit3250.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Embest/Timll DevKit3250 board configuration file
   4  *
   5  * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   6  */
   7
   8 #ifndef __CONFIG_DEVKIT3250_H__
   9 #define __CONFIG_DEVKIT3250_H__
  10
  11 /* SoC and board defines */
  12 #include <linux/sizes.h>
  13 #include <asm/arch/cpu.h>
  14
  15 #define CONFIG_MACH_TYPE                MACH_TYPE_DEVKIT3250
  16
  17 #if !defined(CONFIG_SPL_BUILD)
  18 #define CONFIG_SKIP_LOWLEVEL_INIT
  19 #endif
  20
  21 /*
  22  * Memory configurations
  23  */
  24 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  25 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  26 #define CONFIG_SYS_SDRAM_SIZE           SZ_64M
  27
  28 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  29
  30 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
  31                                          - GENERATED_GBL_DATA_SIZE)
  32
  33 /*
  34  * DMA
  35  */
  36 #if !defined(CONFIG_SPL_BUILD)
  37 #define CONFIG_DMA_LPC32XX
  38 #endif
  39
  40 /*
  41  * I2C
  42  */
  43 #define CONFIG_SYS_I2C_SPEED            100000
  44
  45 /*
  46  * GPIO
  47  */
  48 #define CONFIG_LPC32XX_GPIO
  49
  50 /*
  51  * Ethernet
  52  */
  53 #define CONFIG_RMII
  54 #define CONFIG_LPC32XX_ETH
  55 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  56
  57 /*
  58  * NOR Flash
  59  */
  60 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  61 #define CONFIG_SYS_MAX_FLASH_SECT       71
  62 #define CONFIG_SYS_FLASH_BASE           EMC_CS0_BASE
  63 #define CONFIG_SYS_FLASH_SIZE           SZ_4M
  64
  65 /*
  66  * NAND controller
  67  */
  68 #define CONFIG_SYS_NAND_BASE            SLC_NAND_BASE
  69 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  70 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  71
  72 /*
  73  * NAND chip timings
  74  */
  75 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS        14
  76 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH          66666666
  77 #define CONFIG_LPC32XX_NAND_SLC_WHOLD           200000000
  78 #define CONFIG_LPC32XX_NAND_SLC_WSETUP          50000000
  79 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS        14
  80 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH          66666666
  81 #define CONFIG_LPC32XX_NAND_SLC_RHOLD           200000000
  82 #define CONFIG_LPC32XX_NAND_SLC_RSETUP          50000000
  83
  84 #define CONFIG_SYS_NAND_BLOCK_SIZE              0x20000
  85 #define CONFIG_SYS_NAND_PAGE_SIZE               NAND_LARGE_BLOCK_PAGE_SIZE
  86
  87 /*
  88  * USB
  89  */
  90 #define CONFIG_USB_OHCI_LPC32XX
  91 #define CONFIG_USB_ISP1301_I2C_ADDR             0x2d
  92
  93 /*
  94  * U-Boot General Configurations
  95  */
  96 #define CONFIG_SYS_CBSIZE               1024
  97 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  98
  99 /*
 100  * Pass open firmware flat tree
 101  */
 102
 103 /*
 104  * Environment
 105  */
 106
 107 #define CONFIG_BOOTCOMMAND                      \
 108         "dhcp; "                                \
 109         "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "         \
 110         "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "       \
 111         "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "     \
 112         "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "                  \
 113         "bootm ${loadaddr} - ${dtbaddr}"
 114
 115 #define CONFIG_EXTRA_ENV_SETTINGS               \
 116         "autoload=no\0"                         \
 117         "ethaddr=00:01:90:00:C0:81\0"           \
 118         "dtbaddr=0x81000000\0"                  \
 119         "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"  \
 120         "tftpdir=vladimir/oe/devkit3250\0"      \
 121         "userargs=oops=panic\0"
 122
 123 /*
 124  * U-Boot Commands
 125  */
 126
 127 /*
 128  * Boot Linux
 129  */
 130 #define CONFIG_CMDLINE_TAG
 131 #define CONFIG_SETUP_MEMORY_TAGS
 132
 133 #define CONFIG_BOOTFILE                 "uImage"
 134 #define CONFIG_LOADADDR                 0x80008000
 135
 136 /*
 137  * SPL specific defines
 138  */
 139 /* SPL will be executed at offset 0 */
 140
 141 /* SPL will use SRAM as stack */
 142 #define CONFIG_SPL_STACK                0x0000FFF8
 143
 144 /* Use the framework and generic lib */
 145
 146 /* SPL will use serial */
 147
 148 /* SPL loads an image from NAND */
 149 #define CONFIG_SPL_NAND_RAW_ONLY
 150
 151 #define CONFIG_SPL_NAND_SOFTECC
 152
 153 #define CONFIG_SPL_MAX_SIZE             0x20000
 154 #define CONFIG_SPL_PAD_TO               CONFIG_SPL_MAX_SIZE
 155
 156 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 157 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 158 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 159
 160 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 161 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 162
 163 /* See common/spl/spl.c  spl_set_header_raw_uboot() */
 164 #define CONFIG_SYS_MONITOR_LEN          CONFIG_SYS_NAND_U_BOOT_SIZE
 165
 166 /*
 167  * Include SoC specific configuration
 168  */
 169 #include <asm/arch/config.h>
 170
 171 #endif  /* __CONFIG_DEVKIT3250_H__*/