1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
6 #ifndef _CONFIG_DB_MV7846MP_GP_H
7 #define _CONFIG_DB_MV7846MP_GP_H
10 * High Level Configuration Options (easy to change)
12 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */
15 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
16 * for DDR ECC byte filling in the SPL before loading the main
21 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
23 /* USB/EHCI configuration */
24 #define CONFIG_USB_EHCI_IS_TDI
25 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
27 /* Environment in SPI NOR flash */
29 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
32 #define CONFIG_SYS_SATA_MAX_DEVICE 2
36 #ifndef CONFIG_SPL_BUILD
37 #define CONFIG_PCI_SCAN_SHOW
43 * mv-common.h should be defined after CMD configs since it used them
44 * to enable certain macros
46 #include "mv-common.h"
49 * Memory layout while starting into the bin_hdr via the
52 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
53 * 0x4000.4030 bin_hdr start address
54 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
55 * 0x4007.fffc BootROM stack top
57 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
58 * L2 cache thus cannot be used.
63 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
65 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
66 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
68 #ifdef CONFIG_SPL_BUILD
69 #define CONFIG_SYS_MALLOC_SIMPLE
72 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
73 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
75 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
76 #define CONFIG_SPD_EEPROM 0x4e
77 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
79 #endif /* _CONFIG_DB_MV7846MP_GP_H */