include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  21 #define CONFIG_SYS_OSCIN_FREQ           24000000
  22 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  23 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  24
  25 #ifdef CONFIG_MTD_NOR_FLASH
  26 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  27 #endif
  28
  29 /*
  30  * Memory Info
  31  */
  32 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  33 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  34 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  35 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  36 /* memtest start addr */
  37
  38 /* memtest will be run on 16MB */
  39
  40 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  41         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  42         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  43         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  44         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  45         DAVINCI_SYSCFG_SUSPSRC_I2C)
  46
  47 /*
  48  * PLL configuration
  49  */
  50
  51 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  52 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  53
  54 /*
  55  * DDR2 memory configuration
  56  */
  57 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  58                                         DV_DDR_PHY_EXT_STRBEN | \
  59                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  60
  61 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  62         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  63         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  64         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  65         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  66         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  67         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  68         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  69
  70 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  71 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  72
  73 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  74         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  75         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  76         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  77         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  78         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  79         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  80         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  81         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  82
  83 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  84         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  85         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  86         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  87         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  88         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  89         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  90         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  91
  92 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
  93 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  94
  95 /*
  96  * Serial Driver info
  97  */
  98 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
  99
 100 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 101
 102 /*
 103  * I2C Configuration
 104  */
 105 #ifndef CONFIG_SPL_BUILD
 106 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 107 #endif
 108
 109 /*
 110  * Flash & Environment
 111  */
 112 #ifdef CONFIG_MTD_RAW_NAND
 113 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 114 #define CONFIG_SYS_NAND_PAGE_2K
 115 #define CONFIG_SYS_NAND_CS              3
 116 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 117 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 118 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 119 #undef CONFIG_SYS_NAND_HW_ECC
 120 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 121 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 122 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 123 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 124 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 125 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 126                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 127                                         CONFIG_SYS_MALLOC_LEN -       \
 128                                         GENERATED_GBL_DATA_SIZE)
 129 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 130                                 24, 25, 26, 27, 28, \
 131                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 132                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 133                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 134                                 59, 60, 61, 62, 63 }
 135 #define CONFIG_SYS_NAND_ECCSIZE         512
 136 #define CONFIG_SYS_NAND_ECCBYTES        10
 137 #endif
 138
 139 #ifdef CONFIG_MTD_NOR_FLASH
 140 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 141 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 142 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 143 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 144                + 3)
 145 #endif
 146
 147 /*
 148  * U-Boot general configuration
 149  */
 150
 151 /*
 152  * Linux Information
 153  */
 154 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 155 #define CONFIG_HWCONFIG         /* enable hwconfig */
 156
 157 #define DEFAULT_LINUX_BOOT_ENV \
 158         "loadaddr=0xc0700000\0" \
 159         "fdtaddr=0xc0600000\0" \
 160         "scriptaddr=0xc0600000\0"
 161
 162 #include <environment/ti/mmc.h>
 163
 164 #define CONFIG_EXTRA_ENV_SETTINGS \
 165         DEFAULT_LINUX_BOOT_ENV \
 166         DEFAULT_MMC_TI_ARGS \
 167         "bootpart=0:2\0" \
 168         "bootdir=/boot\0" \
 169         "bootfile=zImage\0" \
 170         "fdtfile=da850-evm.dtb\0" \
 171         "boot_fdt=yes\0" \
 172         "boot_fit=0\0" \
 173         "console=ttyS2,115200n8\0" \
 174         "hwconfig=dsp:wake=yes"
 175
 176 /* USB Configs */
 177 #define CONFIG_USB_OHCI_NEW
 178 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 179
 180 #ifdef CONFIG_SPL_BUILD
 181 /* defines for SPL */
 182 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 183                                                 CONFIG_SYS_MALLOC_LEN)
 184 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 185 #define CONFIG_SPL_STACK        0x8001ff00
 186
 187 #endif
 188
 189 /* Load U-Boot Image From MMC */
 190
 191 /* additions for new relocation code, must added to all boards */
 192 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 193
 194 #include <asm/arch/hardware.h>
 195
 196 #endif /* __CONFIG_H */