include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  21 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  22 #define CONFIG_SYS_OSCIN_FREQ           24000000
  23 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  24 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  25
  26 #ifdef CONFIG_MTD_NOR_FLASH
  27 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  28 #endif
  29
  30 /*
  31  * Memory Info
  32  */
  33 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  34 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  35 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  36 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  37 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  38 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  39 /* memtest start addr */
  40
  41 /* memtest will be run on 16MB */
  42
  43 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  44         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  45         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  46         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  47         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  48         DAVINCI_SYSCFG_SUSPSRC_I2C)
  49
  50 /*
  51  * PLL configuration
  52  */
  53
  54 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  55 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  56
  57 /*
  58  * DDR2 memory configuration
  59  */
  60 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  61                                         DV_DDR_PHY_EXT_STRBEN | \
  62                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  63
  64 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  65         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  66         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  67         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  68         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  69         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  70         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  71         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  72
  73 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  74 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  75
  76 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  77         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  78         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  79         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  80         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  81         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  82         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  83         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  84         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  85
  86 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  87         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  88         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  89         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  90         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  91         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  92         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  93         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  94
  95 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
  96 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  97
  98 /*
  99  * Serial Driver info
 100  */
 101 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 102
 103 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 104
 105 /*
 106  * I2C Configuration
 107  */
 108 #ifndef CONFIG_SPL_BUILD
 109 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 110 #endif
 111
 112 /*
 113  * Flash & Environment
 114  */
 115 #ifdef CONFIG_MTD_RAW_NAND
 116 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 117 #define CONFIG_SYS_NAND_PAGE_2K
 118 #define CONFIG_SYS_NAND_CS              3
 119 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 120 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 121 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 122 #undef CONFIG_SYS_NAND_HW_ECC
 123 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 124 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 125 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 126 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 127 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 128 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 129 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 130 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 131 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 132                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 133                                         CONFIG_SYS_MALLOC_LEN -       \
 134                                         GENERATED_GBL_DATA_SIZE)
 135 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 136                                 24, 25, 26, 27, 28, \
 137                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 138                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 139                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 140                                 59, 60, 61, 62, 63 }
 141 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 142 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 143 #define CONFIG_SYS_NAND_ECCSIZE         512
 144 #define CONFIG_SYS_NAND_ECCBYTES        10
 145 #define CONFIG_SYS_NAND_OOBSIZE         64
 146 #define CONFIG_SPL_NAND_LOAD
 147
 148 #ifndef CONFIG_SPL_BUILD
 149 #define CONFIG_SYS_NAND_SELF_INIT
 150 #endif
 151 #endif
 152
 153 /*
 154  * Network & Ethernet Configuration
 155  */
 156 #ifdef CONFIG_DRIVER_TI_EMAC
 157 #define CONFIG_NET_RETRY_COUNT  10
 158 #endif
 159
 160 #ifdef CONFIG_MTD_NOR_FLASH
 161 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 162 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 163 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 164 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 165 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 166                + 3)
 167 #endif
 168
 169 /*
 170  * U-Boot general configuration
 171  */
 172 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 173 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 174 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 175
 176 /*
 177  * Linux Information
 178  */
 179 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 180 #define CONFIG_HWCONFIG         /* enable hwconfig */
 181 #define CONFIG_CMDLINE_TAG
 182 #define CONFIG_REVISION_TAG
 183 #define CONFIG_SETUP_MEMORY_TAGS
 184
 185 #define CONFIG_BOOTCOMMAND \
 186                 "run envboot; " \
 187                 "run mmcboot; "
 188
 189 #define DEFAULT_LINUX_BOOT_ENV \
 190         "loadaddr=0xc0700000\0" \
 191         "fdtaddr=0xc0600000\0" \
 192         "scriptaddr=0xc0600000\0"
 193
 194 #include <environment/ti/mmc.h>
 195
 196 #define CONFIG_EXTRA_ENV_SETTINGS \
 197         DEFAULT_LINUX_BOOT_ENV \
 198         DEFAULT_MMC_TI_ARGS \
 199         "bootpart=0:2\0" \
 200         "bootdir=/boot\0" \
 201         "bootfile=zImage\0" \
 202         "fdtfile=da850-evm.dtb\0" \
 203         "boot_fdt=yes\0" \
 204         "boot_fit=0\0" \
 205         "console=ttyS2,115200n8\0" \
 206         "hwconfig=dsp:wake=yes"
 207
 208 #ifdef CONFIG_CMD_BDI
 209 #define CONFIG_CLOCKS
 210 #endif
 211
 212 /* USB Configs */
 213 #define CONFIG_USB_OHCI_NEW
 214 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 215
 216 #ifndef CONFIG_MTD_NOR_FLASH
 217 #define CONFIG_SPL_PAD_TO       32768
 218 #endif
 219
 220 #ifdef CONFIG_SPL_BUILD
 221 /* defines for SPL */
 222 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 223                                                 CONFIG_SYS_MALLOC_LEN)
 224 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 225 #define CONFIG_SPL_STACK        0x8001ff00
 226 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 227
 228 #endif
 229
 230 /* Load U-Boot Image From MMC */
 231
 232 /* additions for new relocation code, must added to all boards */
 233 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 234
 235 #ifdef CONFIG_MTD_NOR_FLASH
 236 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 237 #else
 238 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 239                                         GENERATED_GBL_DATA_SIZE)
 240 #endif /* CONFIG_MTD_NOR_FLASH */
 241
 242 #include <asm/arch/hardware.h>
 243
 244 #endif /* __CONFIG_H */