include/configs/da850evm.h

   1 /*
   2  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * Based on davinci_dvevm.h. Original Copyrights follow:
   5  *
   6  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * Board
  16  */
  17 #define CONFIG_DRIVER_TI_EMAC
  18 /* check if direct NOR boot config is used */
  19 #ifndef CONFIG_DIRECT_NOR_BOOT
  20 #define CONFIG_USE_SPIFLASH
  21 #endif
  22
  23
  24 /*
  25  * SoC Configuration
  26  */
  27 #define CONFIG_MACH_DAVINCI_DA850_EVM
  28 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
  29 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
  30 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  31 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  32 #define CONFIG_SYS_OSCIN_FREQ           24000000
  33 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  34 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  35 #define CONFIG_SYS_DA850_PLL_INIT
  36 #define CONFIG_SYS_DA850_DDR_INIT
  37
  38 #ifdef CONFIG_DIRECT_NOR_BOOT
  39 #define CONFIG_ARCH_CPU_INIT
  40 #define CONFIG_DA8XX_GPIO
  41 #define CONFIG_SYS_TEXT_BASE            0x60000000
  42 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  43 #define CONFIG_DA850_LOWLEVEL
  44 #else
  45 #define CONFIG_SYS_TEXT_BASE            0xc1080000
  46 #endif
  47
  48 /*
  49  * Memory Info
  50  */
  51 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  52 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  53 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  54 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  55
  56 /* memtest start addr */
  57 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  58
  59 /* memtest will be run on 16MB */
  60 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  61
  62 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  63
  64 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  65         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  66         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  67         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  68         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  69         DAVINCI_SYSCFG_SUSPSRC_I2C)
  70
  71 /*
  72  * PLL configuration
  73  */
  74 #define CONFIG_SYS_DV_CLKMODE          0
  75 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
  76 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
  77 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
  78 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
  79 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
  80 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
  81 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
  82 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
  83
  84 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
  85 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
  86 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
  87 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
  88
  89 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  90 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  91
  92 /*
  93  * DDR2 memory configuration
  94  */
  95 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  96                                         DV_DDR_PHY_EXT_STRBEN | \
  97                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  98
  99 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
 100         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
 101         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
 102         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
 103         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
 104         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
 105         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
 106         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 107
 108 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
 109 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
 110
 111 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
 112         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
 113         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
 114         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
 115         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
 116         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
 117         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
 118         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
 119         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
 120
 121 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
 122         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
 123         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
 124         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
 125         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
 126         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 127         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 128         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 129
 130 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 131 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 132
 133 /*
 134  * Serial Driver info
 135  */
 136 #define CONFIG_SYS_NS16550_SERIAL
 137 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 138 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 139 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 140 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
 141 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
 142
 143 #define CONFIG_SPI
 144 #define CONFIG_CMD_SF
 145 #define CONFIG_DAVINCI_SPI
 146 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 147 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 148 #define CONFIG_SF_DEFAULT_SPEED         30000000
 149 #define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
 150
 151 #ifdef CONFIG_USE_SPIFLASH
 152 #define CONFIG_SPL_SPI_SUPPORT
 153 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 154 #define CONFIG_SPL_SPI_LOAD
 155 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 156 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
 157 #endif
 158
 159 /*
 160  * I2C Configuration
 161  */
 162 #define CONFIG_SYS_I2C
 163 #define CONFIG_SYS_I2C_DAVINCI
 164 #define CONFIG_SYS_DAVINCI_I2C_SPEED            25000
 165 #define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
 166 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 167
 168 /*
 169  * Flash & Environment
 170  */
 171 #ifdef CONFIG_USE_NAND
 172 #undef CONFIG_ENV_IS_IN_FLASH
 173 #define CONFIG_NAND_DAVINCI
 174 #define CONFIG_SYS_NO_FLASH
 175 #define CONFIG_ENV_IS_IN_NAND           /* U-Boot env in NAND Flash  */
 176 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 177 #define CONFIG_ENV_SIZE                 (128 << 10)
 178 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 179 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 180 #define CONFIG_SYS_NAND_PAGE_2K
 181 #define CONFIG_SYS_NAND_CS              3
 182 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 183 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 184 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 185 #undef CONFIG_SYS_NAND_HW_ECC
 186 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 187 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 188 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 189 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 190 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 191 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x28000
 192 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 193 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 194 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 195 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 196                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 197                                         CONFIG_SYS_MALLOC_LEN -       \
 198                                         GENERATED_GBL_DATA_SIZE)
 199 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 200                                 24, 25, 26, 27, 28, \
 201                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 202                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 203                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 204                                 59, 60, 61, 62, 63 }
 205 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 206 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 207 #define CONFIG_SYS_NAND_ECCSIZE         512
 208 #define CONFIG_SYS_NAND_ECCBYTES        10
 209 #define CONFIG_SYS_NAND_OOBSIZE         64
 210 #define CONFIG_SPL_NAND_SUPPORT
 211 #define CONFIG_SPL_NAND_BASE
 212 #define CONFIG_SPL_NAND_DRIVERS
 213 #define CONFIG_SPL_NAND_ECC
 214 #define CONFIG_SPL_NAND_SIMPLE
 215 #define CONFIG_SPL_NAND_LOAD
 216 #endif
 217
 218 /*
 219  * Network & Ethernet Configuration
 220  */
 221 #ifdef CONFIG_DRIVER_TI_EMAC
 222 #define CONFIG_MII
 223 #define CONFIG_BOOTP_DNS
 224 #define CONFIG_BOOTP_DNS2
 225 #define CONFIG_BOOTP_SEND_HOSTNAME
 226 #define CONFIG_NET_RETRY_COUNT  10
 227 #endif
 228
 229 #ifdef CONFIG_USE_NOR
 230 #define CONFIG_ENV_IS_IN_FLASH
 231 #define CONFIG_FLASH_CFI_DRIVER
 232 #define CONFIG_SYS_FLASH_CFI
 233 #define CONFIG_SYS_FLASH_PROTECTION
 234 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 235 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 236 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
 237 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
 238 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 239 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 240 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 241                + 3)
 242 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 243 #endif
 244
 245 #ifdef CONFIG_USE_SPIFLASH
 246 #undef CONFIG_ENV_IS_IN_FLASH
 247 #undef CONFIG_ENV_IS_IN_NAND
 248 #define CONFIG_ENV_IS_IN_SPI_FLASH
 249 #define CONFIG_ENV_SIZE                 (64 << 10)
 250 #define CONFIG_ENV_OFFSET               (512 << 10)
 251 #define CONFIG_ENV_SECT_SIZE            (64 << 10)
 252 #define CONFIG_SYS_NO_FLASH
 253 #endif
 254
 255 /*
 256  * U-Boot general configuration
 257  */
 258 #define CONFIG_MISC_INIT_R
 259 #define CONFIG_BOARD_EARLY_INIT_F
 260 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 261 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 262 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 263 #define CONFIG_SYS_MAXARGS      16 /* max number of command args */
 264 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 265 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 266 #define CONFIG_VERSION_VARIABLE
 267 #define CONFIG_AUTO_COMPLETE
 268 #define CONFIG_SYS_HUSH_PARSER
 269 #define CONFIG_CMDLINE_EDITING
 270 #define CONFIG_SYS_LONGHELP
 271 #define CONFIG_CRC32_VERIFY
 272 #define CONFIG_MX_CYCLIC
 273 #define CONFIG_OF_LIBFDT
 274
 275 /*
 276  * Linux Information
 277  */
 278 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 279 #define CONFIG_HWCONFIG         /* enable hwconfig */
 280 #define CONFIG_CMDLINE_TAG
 281 #define CONFIG_REVISION_TAG
 282 #define CONFIG_SETUP_MEMORY_TAGS
 283 #define CONFIG_BOOTARGS         \
 284         "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
 285 #define CONFIG_BOOTDELAY        3
 286 #define CONFIG_EXTRA_ENV_SETTINGS       "hwconfig=dsp:wake=yes"
 287
 288 /*
 289  * U-Boot commands
 290  */
 291 #define CONFIG_CMD_ENV
 292 #define CONFIG_CMD_ASKENV
 293 #define CONFIG_CMD_DHCP
 294 #define CONFIG_CMD_DIAG
 295 #define CONFIG_CMD_MII
 296 #define CONFIG_CMD_PING
 297 #define CONFIG_CMD_SAVES
 298
 299 #ifdef CONFIG_CMD_BDI
 300 #define CONFIG_CLOCKS
 301 #endif
 302
 303 #ifndef CONFIG_DRIVER_TI_EMAC
 304 #undef CONFIG_CMD_DHCP
 305 #undef CONFIG_CMD_MII
 306 #undef CONFIG_CMD_PING
 307 #endif
 308
 309 #ifdef CONFIG_USE_NAND
 310 #define CONFIG_CMD_NAND
 311
 312 #define CONFIG_CMD_MTDPARTS
 313 #define CONFIG_MTD_DEVICE
 314 #define CONFIG_MTD_PARTITIONS
 315 #define CONFIG_LZO
 316 #define CONFIG_RBTREE
 317 #define CONFIG_CMD_UBI
 318 #define CONFIG_CMD_UBIFS
 319 #endif
 320
 321 #ifdef CONFIG_USE_SPIFLASH
 322 #define CONFIG_CMD_SPI
 323 #endif
 324
 325 #if !defined(CONFIG_USE_NAND) && \
 326         !defined(CONFIG_USE_NOR) && \
 327         !defined(CONFIG_USE_SPIFLASH)
 328 #define CONFIG_ENV_IS_NOWHERE
 329 #define CONFIG_SYS_NO_FLASH
 330 #define CONFIG_ENV_SIZE         (16 << 10)
 331 #undef CONFIG_CMD_ENV
 332 #endif
 333
 334 /* SD/MMC configuration */
 335 #ifndef CONFIG_USE_NOR
 336 #define CONFIG_MMC
 337 #define CONFIG_DAVINCI_MMC_SD1
 338 #define CONFIG_GENERIC_MMC
 339 #define CONFIG_DAVINCI_MMC
 340 #endif
 341
 342 /*
 343  * Enable MMC commands only when
 344  * MMC support is present
 345  */
 346 #ifdef CONFIG_MMC
 347 #define CONFIG_DOS_PARTITION
 348 #define CONFIG_CMD_EXT2
 349 #define CONFIG_CMD_FAT
 350 #define CONFIG_CMD_MMC
 351 #endif
 352
 353 #ifndef CONFIG_DIRECT_NOR_BOOT
 354 /* defines for SPL */
 355 #define CONFIG_SPL_FRAMEWORK
 356 #define CONFIG_SPL_BOARD_INIT
 357 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 358                                                 CONFIG_SYS_MALLOC_LEN)
 359 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 360 #define CONFIG_SPL_SPI_SUPPORT
 361 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 362 #define CONFIG_SPL_SPI_LOAD
 363 #define CONFIG_SPL_SERIAL_SUPPORT
 364 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 365 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 366 #define CONFIG_SPL_LDSCRIPT     "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
 367 #define CONFIG_SPL_STACK        0x8001ff00
 368 #define CONFIG_SPL_TEXT_BASE    0x80000000
 369 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 370 #define CONFIG_SPL_PAD_TO       32768
 371 #endif
 372
 373 /* Load U-Boot Image From MMC */
 374 #ifdef CONFIG_SPL_MMC_LOAD
 375 #define CONFIG_SPL_MMC_SUPPORT
 376 #define CONFIG_SPL_LIBDISK_SUPPORT
 377 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
 378 #undef CONFIG_SPL_SPI_SUPPORT
 379 #undef CONFIG_SPL_SPI_LOAD
 380 #endif
 381
 382 /* additions for new relocation code, must added to all boards */
 383 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 384
 385 #ifdef CONFIG_DIRECT_NOR_BOOT
 386 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 387 #else
 388 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 389                                         GENERATED_GBL_DATA_SIZE)
 390 #endif /* CONFIG_DIRECT_NOR_BOOT */
 391 #endif /* __CONFIG_H */