include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #ifdef CONFIG_NXP_ESBC
  19 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  21 #ifdef CONFIG_MTD_RAW_NAND
  22 #define CONFIG_RAMBOOT_NAND
  23 #endif
  24 #define CONFIG_BOOTSCRIPT_COPY_RAM
  25 #else
  26 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  28 #endif
  29 #endif
  30
  31 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  32 /* Set 1M boot space */
  33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  34 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  35                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  37 #endif
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  41
  42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  43 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  44 #endif
  45
  46 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  47 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  48 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  49 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  50
  51 #if defined(CONFIG_SPIFLASH)
  52 #elif defined(CONFIG_SDCARD)
  53 #define CONFIG_FSL_FIXED_MMC_LOCATION
  54 #endif
  55
  56 /*
  57  * These can be toggled for performance analysis, otherwise use default.
  58  */
  59 #define CONFIG_SYS_CACHE_STASHING
  60 #define CONFIG_BACKSIDE_L2_CACHE
  61 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  62 #ifdef CONFIG_DDR_ECC
  63 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  64 #endif
  65
  66 #define CONFIG_ENABLE_36BIT_PHYS
  67
  68 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  69
  70 /*
  71  *  Config the L3 Cache as L3 SRAM
  72  */
  73 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  74 #ifdef CONFIG_PHYS_64BIT
  75 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  76 #else
  77 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  78 #endif
  79 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  80 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  81
  82 #ifdef CONFIG_PHYS_64BIT
  83 #define CONFIG_SYS_DCSRBAR              0xf0000000
  84 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  85 #endif
  86
  87 /* EEPROM */
  88 #define CONFIG_SYS_I2C_EEPROM_NXID
  89 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  90
  91 /*
  92  * DDR Setup
  93  */
  94 #define CONFIG_VERY_BIG_RAM
  95 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  96 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  97
  98 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  99
 100 #define CONFIG_SYS_SPD_BUS_NUM  1
 101 #define SPD_EEPROM_ADDRESS1     0x51
 102 #define SPD_EEPROM_ADDRESS2     0x52
 103 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 104 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 105
 106 /*
 107  * Local Bus Definitions
 108  */
 109
 110 /* Set the local bus clock 1/8 of platform clock */
 111 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 112
 113 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 114 #ifdef CONFIG_PHYS_64BIT
 115 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 116 #else
 117 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 118 #endif
 119
 120 #define CONFIG_SYS_FLASH_BR_PRELIM \
 121                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 122                  | BR_PS_16 | BR_V)
 123 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 124                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 125
 126 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 127 #ifdef CONFIG_PHYS_64BIT
 128 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 129 #else
 130 #define PIXIS_BASE_PHYS         PIXIS_BASE
 131 #endif
 132
 133 #define PIXIS_LBMAP_SWITCH      7
 134 #define PIXIS_LBMAP_MASK        0xf0
 135 #define PIXIS_LBMAP_SHIFT       4
 136 #define PIXIS_LBMAP_ALTBANK     0x40
 137
 138 #define CONFIG_SYS_FLASH_QUIET_TEST
 139 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 140
 141 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 142 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 143 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 144
 145 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 146
 147 #if defined(CONFIG_RAMBOOT_PBL)
 148 #define CONFIG_SYS_RAMBOOT
 149 #endif
 150
 151 /* Nand Flash */
 152 #ifdef CONFIG_NAND_FSL_ELBC
 153 #define CONFIG_SYS_NAND_BASE            0xffa00000
 154 #ifdef CONFIG_PHYS_64BIT
 155 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 156 #else
 157 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 158 #endif
 159
 160 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 161 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 162
 163 /* NAND flash config */
 164 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 165                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 166                                | BR_PS_8               /* Port Size = 8 bit */ \
 167                                | BR_MS_FCM             /* MSEL = FCM */ \
 168                                | BR_V)                 /* valid */
 169 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 170                                | OR_FCM_PGS            /* Large Page*/ \
 171                                | OR_FCM_CSCT \
 172                                | OR_FCM_CST \
 173                                | OR_FCM_CHT \
 174                                | OR_FCM_SCY_1 \
 175                                | OR_FCM_TRLX \
 176                                | OR_FCM_EHTR)
 177 #endif /* CONFIG_NAND_FSL_ELBC */
 178
 179 #define CONFIG_SYS_FLASH_EMPTY_INFO
 180 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 181
 182 #define CONFIG_HWCONFIG
 183
 184 /* define to use L1 as initial stack */
 185 #define CONFIG_L1_INIT_RAM
 186 #define CONFIG_SYS_INIT_RAM_LOCK
 187 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 188 #ifdef CONFIG_PHYS_64BIT
 189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 190 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 191 /* The assembler doesn't like typecast */
 192 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 193         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 194           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 195 #else
 196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 199 #endif
 200 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 201
 202 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 203 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 204
 205 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 206
 207 /* Serial Port - controlled on board with jumper J8
 208  * open - index 2
 209  * shorted - index 1
 210  */
 211 #define CONFIG_SYS_NS16550_SERIAL
 212 #define CONFIG_SYS_NS16550_REG_SIZE     1
 213 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 214
 215 #define CONFIG_SYS_BAUDRATE_TABLE       \
 216         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 217
 218 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 219 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 220 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 221 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 222
 223 /* I2C */
 224
 225 /*
 226  * RapidIO
 227  */
 228 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 229 #ifdef CONFIG_PHYS_64BIT
 230 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 231 #else
 232 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 233 #endif
 234 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 235
 236 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 237 #ifdef CONFIG_PHYS_64BIT
 238 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 239 #else
 240 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 241 #endif
 242 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 243
 244 /*
 245  * for slave u-boot IMAGE instored in master memory space,
 246  * PHYS must be aligned based on the SIZE
 247  */
 248 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 249 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 250 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 251 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 252 /*
 253  * for slave UCODE and ENV instored in master memory space,
 254  * PHYS must be aligned based on the SIZE
 255  */
 256 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 257 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 258 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 259
 260 /* slave core release by master*/
 261 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 262 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 263
 264 /*
 265  * SRIO_PCIE_BOOT - SLAVE
 266  */
 267 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 268 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 269 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 270                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 271 #endif
 272
 273 /*
 274  * eSPI - Enhanced SPI
 275  */
 276
 277 /*
 278  * General PCI
 279  * Memory space is mapped 1-1, but I/O space must start from 0.
 280  */
 281
 282 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 283 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 284 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 285 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 286 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 287
 288 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 289 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 290 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 291 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 292 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 293
 294 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 295 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 296 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 297 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 298 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 299
 300 /* controller 4, Base address 203000 */
 301 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 302 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 303
 304 /* Qman/Bman */
 305 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 306 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 307 #ifdef CONFIG_PHYS_64BIT
 308 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 309 #else
 310 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 311 #endif
 312 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 313 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 314 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 315 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 316 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 317 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 318                                         CONFIG_SYS_BMAN_CENA_SIZE)
 319 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 320 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 321 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 322 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 323 #ifdef CONFIG_PHYS_64BIT
 324 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 325 #else
 326 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 327 #endif
 328 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 329 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 330 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 331 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 332 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 333 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 334                                         CONFIG_SYS_QMAN_CENA_SIZE)
 335 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 336 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 337
 338 #define CONFIG_SYS_DPAA_FMAN
 339 #define CONFIG_SYS_DPAA_PME
 340 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 341
 342 #ifdef CONFIG_PCI
 343 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 344 #endif  /* CONFIG_PCI */
 345
 346 /* SATA */
 347 #ifdef CONFIG_FSL_SATA_V2
 348 #define CONFIG_SATA1
 349 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 350 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 351 #define CONFIG_SATA2
 352 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 353 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 354
 355 #define CONFIG_LBA48
 356 #endif
 357
 358 #ifdef CONFIG_FMAN_ENET
 359 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 360 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 361 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 362 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 363 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 364
 365 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 366 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 367 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 368 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 369 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 370
 371 #define CONFIG_SYS_TBIPA_VALUE  8
 372 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 373 #endif
 374
 375 /*
 376  * Environment
 377  */
 378 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 379 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 380
 381 /*
 382 * USB
 383 */
 384 #define CONFIG_HAS_FSL_DR_USB
 385 #define CONFIG_HAS_FSL_MPH_USB
 386
 387 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 388 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 389 #endif
 390
 391 #ifdef CONFIG_MMC
 392 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 393 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 394 #endif
 395
 396 /*
 397  * Miscellaneous configurable options
 398  */
 399
 400 /*
 401  * For booting Linux, the board info and command line data
 402  * have to be in the first 64 MB of memory, since this is
 403  * the maximum mapped by the Linux kernel during initialization.
 404  */
 405 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 406 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 407
 408 /*
 409  * Environment Configuration
 410  */
 411 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 412 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 413
 414 #ifdef CONFIG_TARGET_P4080DS
 415 #define __USB_PHY_TYPE  ulpi
 416 #else
 417 #define __USB_PHY_TYPE  utmi
 418 #endif
 419
 420 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 421         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 422         "bank_intlv=cs0_cs1;"                                   \
 423         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 424         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 425         "netdev=eth0\0"                                         \
 426         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 427         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 428         "tftpflash=tftpboot $loadaddr $uboot && "               \
 429         "protect off $ubootaddr +$filesize && "                 \
 430         "erase $ubootaddr +$filesize && "                       \
 431         "cp.b $loadaddr $ubootaddr $filesize && "               \
 432         "protect on $ubootaddr +$filesize && "                  \
 433         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 434         "consoledev=ttyS0\0"                                    \
 435         "ramdiskaddr=2000000\0"                                 \
 436         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 437         "fdtaddr=1e00000\0"                                     \
 438         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 439         "bdev=sda3\0"
 440
 441 #include <asm/fsl_secure_boot.h>
 442
 443 #endif  /* __CONFIG_H */