include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #ifdef CONFIG_NXP_ESBC
  19 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  21 #ifdef CONFIG_MTD_RAW_NAND
  22 #define CONFIG_RAMBOOT_NAND
  23 #endif
  24 #define CONFIG_BOOTSCRIPT_COPY_RAM
  25 #else
  26 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  28 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  29 #if defined(CONFIG_TARGET_P3041DS)
  30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  31 #elif defined(CONFIG_TARGET_P4080DS)
  32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  33 #elif defined(CONFIG_TARGET_P5020DS)
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  35 #elif defined(CONFIG_TARGET_P5040DS)
  36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  37 #endif
  38 #endif
  39 #endif
  40
  41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  42 /* Set 1M boot space */
  43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  45                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  47 #endif
  48
  49 /* High Level Configuration Options */
  50 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  51
  52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  53 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  54 #endif
  55
  56 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  57 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  58 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  59 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  60 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  61
  62 #if defined(CONFIG_SPIFLASH)
  63 #elif defined(CONFIG_SDCARD)
  64 #define CONFIG_FSL_FIXED_MMC_LOCATION
  65 #define CONFIG_SYS_MMC_ENV_DEV          0
  66 #endif
  67
  68 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  69
  70 /*
  71  * These can be toggled for performance analysis, otherwise use default.
  72  */
  73 #define CONFIG_SYS_CACHE_STASHING
  74 #define CONFIG_BACKSIDE_L2_CACHE
  75 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  76 #define CONFIG_BTB                      /* toggle branch predition */
  77 #define CONFIG_DDR_ECC
  78 #ifdef CONFIG_DDR_ECC
  79 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  80 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  81 #endif
  82
  83 #define CONFIG_ENABLE_36BIT_PHYS
  84
  85 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  86
  87 /*
  88  *  Config the L3 Cache as L3 SRAM
  89  */
  90 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  91 #ifdef CONFIG_PHYS_64BIT
  92 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  93 #else
  94 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  95 #endif
  96 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  97 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  98
  99 #ifdef CONFIG_PHYS_64BIT
 100 #define CONFIG_SYS_DCSRBAR              0xf0000000
 101 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 102 #endif
 103
 104 /* EEPROM */
 105 #define CONFIG_ID_EEPROM
 106 #define CONFIG_SYS_I2C_EEPROM_NXID
 107 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 108 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 109 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 110
 111 /*
 112  * DDR Setup
 113  */
 114 #define CONFIG_VERY_BIG_RAM
 115 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 116 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 117
 118 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 119 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 120
 121 #define CONFIG_DDR_SPD
 122
 123 #define CONFIG_SYS_SPD_BUS_NUM  1
 124 #define SPD_EEPROM_ADDRESS1     0x51
 125 #define SPD_EEPROM_ADDRESS2     0x52
 126 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 127 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 128
 129 /*
 130  * Local Bus Definitions
 131  */
 132
 133 /* Set the local bus clock 1/8 of platform clock */
 134 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 135
 136 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 137 #ifdef CONFIG_PHYS_64BIT
 138 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 139 #else
 140 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 141 #endif
 142
 143 #define CONFIG_SYS_FLASH_BR_PRELIM \
 144                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 145                  | BR_PS_16 | BR_V)
 146 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 147                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 148
 149 #define CONFIG_SYS_BR1_PRELIM \
 150         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 151 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 152
 153 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 154 #ifdef CONFIG_PHYS_64BIT
 155 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 156 #else
 157 #define PIXIS_BASE_PHYS         PIXIS_BASE
 158 #endif
 159
 160 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 161 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 162
 163 #define PIXIS_LBMAP_SWITCH      7
 164 #define PIXIS_LBMAP_MASK        0xf0
 165 #define PIXIS_LBMAP_SHIFT       4
 166 #define PIXIS_LBMAP_ALTBANK     0x40
 167
 168 #define CONFIG_SYS_FLASH_QUIET_TEST
 169 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 170
 171 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 172 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 173 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 174 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 175
 176 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 177
 178 #if defined(CONFIG_RAMBOOT_PBL)
 179 #define CONFIG_SYS_RAMBOOT
 180 #endif
 181
 182 /* Nand Flash */
 183 #ifdef CONFIG_NAND_FSL_ELBC
 184 #define CONFIG_SYS_NAND_BASE            0xffa00000
 185 #ifdef CONFIG_PHYS_64BIT
 186 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 187 #else
 188 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 189 #endif
 190
 191 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 192 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 193 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 194
 195 /* NAND flash config */
 196 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 197                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 198                                | BR_PS_8               /* Port Size = 8 bit */ \
 199                                | BR_MS_FCM             /* MSEL = FCM */ \
 200                                | BR_V)                 /* valid */
 201 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 202                                | OR_FCM_PGS            /* Large Page*/ \
 203                                | OR_FCM_CSCT \
 204                                | OR_FCM_CST \
 205                                | OR_FCM_CHT \
 206                                | OR_FCM_SCY_1 \
 207                                | OR_FCM_TRLX \
 208                                | OR_FCM_EHTR)
 209
 210 #ifdef CONFIG_MTD_RAW_NAND
 211 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 212 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 213 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 214 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 215 #else
 216 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 217 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 218 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 219 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 220 #endif
 221 #else
 222 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 223 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 224 #endif /* CONFIG_NAND_FSL_ELBC */
 225
 226 #define CONFIG_SYS_FLASH_EMPTY_INFO
 227 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 228 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 229
 230 #define CONFIG_HWCONFIG
 231
 232 /* define to use L1 as initial stack */
 233 #define CONFIG_L1_INIT_RAM
 234 #define CONFIG_SYS_INIT_RAM_LOCK
 235 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 236 #ifdef CONFIG_PHYS_64BIT
 237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 238 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 239 /* The assembler doesn't like typecast */
 240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 241         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 242           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 243 #else
 244 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 245 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 246 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 247 #endif
 248 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 249
 250 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 251 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 252
 253 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 254 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 255
 256 /* Serial Port - controlled on board with jumper J8
 257  * open - index 2
 258  * shorted - index 1
 259  */
 260 #define CONFIG_SYS_NS16550_SERIAL
 261 #define CONFIG_SYS_NS16550_REG_SIZE     1
 262 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 263
 264 #define CONFIG_SYS_BAUDRATE_TABLE       \
 265         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 266
 267 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 268 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 269 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 270 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 271
 272 /* I2C */
 273 #ifndef CONFIG_DM_I2C
 274 #define CONFIG_SYS_I2C
 275 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 276 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 277 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 278 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 279 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 280 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 281 #else
 282 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 283 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 284 #endif
 285 #define CONFIG_SYS_I2C_FSL
 286
 287 /*
 288  * RapidIO
 289  */
 290 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 291 #ifdef CONFIG_PHYS_64BIT
 292 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 293 #else
 294 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 295 #endif
 296 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 297
 298 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 299 #ifdef CONFIG_PHYS_64BIT
 300 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 301 #else
 302 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 303 #endif
 304 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 305
 306 /*
 307  * for slave u-boot IMAGE instored in master memory space,
 308  * PHYS must be aligned based on the SIZE
 309  */
 310 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 311 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 312 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 313 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 314 /*
 315  * for slave UCODE and ENV instored in master memory space,
 316  * PHYS must be aligned based on the SIZE
 317  */
 318 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 319 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 320 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 321
 322 /* slave core release by master*/
 323 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 324 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 325
 326 /*
 327  * SRIO_PCIE_BOOT - SLAVE
 328  */
 329 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 330 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 331 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 332                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 333 #endif
 334
 335 /*
 336  * eSPI - Enhanced SPI
 337  */
 338
 339 /*
 340  * General PCI
 341  * Memory space is mapped 1-1, but I/O space must start from 0.
 342  */
 343
 344 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 345 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 346 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 347 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 348 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 349
 350 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 351 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 352 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 353 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 354 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 355
 356 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 357 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 358 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 359 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 360 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 361
 362 /* controller 4, Base address 203000 */
 363 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 364 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 365
 366 /* Qman/Bman */
 367 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 368 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 369 #ifdef CONFIG_PHYS_64BIT
 370 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 371 #else
 372 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 373 #endif
 374 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 375 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 376 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 377 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 378 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 379 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 380                                         CONFIG_SYS_BMAN_CENA_SIZE)
 381 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 382 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 383 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 384 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 385 #ifdef CONFIG_PHYS_64BIT
 386 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 387 #else
 388 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 389 #endif
 390 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 391 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 392 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 393 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 394 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 395 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 396                                         CONFIG_SYS_QMAN_CENA_SIZE)
 397 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 398 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 399
 400 #define CONFIG_SYS_DPAA_FMAN
 401 #define CONFIG_SYS_DPAA_PME
 402 /* Default address of microcode for the Linux Fman driver */
 403 #if defined(CONFIG_SPIFLASH)
 404 /*
 405  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 406  * env, so we got 0x110000.
 407  */
 408 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 409 #elif defined(CONFIG_SDCARD)
 410 /*
 411  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 412  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 413  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 414  */
 415 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 416 #elif defined(CONFIG_MTD_RAW_NAND)
 417 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 418 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 419 /*
 420  * Slave has no ucode locally, it can fetch this from remote. When implementing
 421  * in two corenet boards, slave's ucode could be stored in master's memory
 422  * space, the address can be mapped from slave TLB->slave LAW->
 423  * slave SRIO or PCIE outbound window->master inbound window->
 424  * master LAW->the ucode address in master's memory space.
 425  */
 426 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 427 #else
 428 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 429 #endif
 430 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 431 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 432
 433 #ifdef CONFIG_PCI
 434 #if !defined(CONFIG_DM_PCI)
 435 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 436 #define CONFIG_PCI_INDIRECT_BRIDGE
 437 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 438 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 439 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 440 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 441 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 442 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 443 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 444 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 445 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 446 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 447 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 448 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 449 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 450 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 451 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 452 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 453 #endif
 454
 455 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 456 #endif  /* CONFIG_PCI */
 457
 458 /* SATA */
 459 #ifdef CONFIG_FSL_SATA_V2
 460 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 461 #define CONFIG_SATA1
 462 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 463 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 464 #define CONFIG_SATA2
 465 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 466 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 467
 468 #define CONFIG_LBA48
 469 #endif
 470
 471 #ifdef CONFIG_FMAN_ENET
 472 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 473 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 474 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 475 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 476 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 477
 478 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 479 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 480 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 481 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 482 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 483
 484 #define CONFIG_SYS_TBIPA_VALUE  8
 485 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 486 #endif
 487
 488 /*
 489  * Environment
 490  */
 491 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 492 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 493
 494 /*
 495 * USB
 496 */
 497 #define CONFIG_HAS_FSL_DR_USB
 498 #define CONFIG_HAS_FSL_MPH_USB
 499
 500 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 501 #define CONFIG_USB_EHCI_FSL
 502 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 503 #endif
 504
 505 #ifdef CONFIG_MMC
 506 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 507 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 508 #endif
 509
 510 /*
 511  * Miscellaneous configurable options
 512  */
 513 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 514
 515 /*
 516  * For booting Linux, the board info and command line data
 517  * have to be in the first 64 MB of memory, since this is
 518  * the maximum mapped by the Linux kernel during initialization.
 519  */
 520 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 521 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 522
 523 #ifdef CONFIG_CMD_KGDB
 524 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 525 #endif
 526
 527 /*
 528  * Environment Configuration
 529  */
 530 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 531 #define CONFIG_BOOTFILE         "uImage"
 532 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 533
 534 /* default location for tftp and bootm */
 535 #define CONFIG_LOADADDR         1000000
 536
 537 #ifdef CONFIG_TARGET_P4080DS
 538 #define __USB_PHY_TYPE  ulpi
 539 #else
 540 #define __USB_PHY_TYPE  utmi
 541 #endif
 542
 543 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 544         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 545         "bank_intlv=cs0_cs1;"                                   \
 546         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 547         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 548         "netdev=eth0\0"                                         \
 549         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 550         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 551         "tftpflash=tftpboot $loadaddr $uboot && "               \
 552         "protect off $ubootaddr +$filesize && "                 \
 553         "erase $ubootaddr +$filesize && "                       \
 554         "cp.b $loadaddr $ubootaddr $filesize && "               \
 555         "protect on $ubootaddr +$filesize && "                  \
 556         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 557         "consoledev=ttyS0\0"                                    \
 558         "ramdiskaddr=2000000\0"                                 \
 559         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 560         "fdtaddr=1e00000\0"                                     \
 561         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 562         "bdev=sda3\0"
 563
 564 #define CONFIG_HDBOOT                                   \
 565         "setenv bootargs root=/dev/$bdev rw "           \
 566         "console=$consoledev,$baudrate $othbootargs;"   \
 567         "tftp $loadaddr $bootfile;"                     \
 568         "tftp $fdtaddr $fdtfile;"                       \
 569         "bootm $loadaddr - $fdtaddr"
 570
 571 #define CONFIG_NFSBOOTCOMMAND                   \
 572         "setenv bootargs root=/dev/nfs rw "     \
 573         "nfsroot=$serverip:$rootpath "          \
 574         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 575         "console=$consoledev,$baudrate $othbootargs;"   \
 576         "tftp $loadaddr $bootfile;"             \
 577         "tftp $fdtaddr $fdtfile;"               \
 578         "bootm $loadaddr - $fdtaddr"
 579
 580 #define CONFIG_RAMBOOTCOMMAND                           \
 581         "setenv bootargs root=/dev/ram rw "             \
 582         "console=$consoledev,$baudrate $othbootargs;"   \
 583         "tftp $ramdiskaddr $ramdiskfile;"               \
 584         "tftp $loadaddr $bootfile;"                     \
 585         "tftp $fdtaddr $fdtfile;"                       \
 586         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 587
 588 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 589
 590 #include <asm/fsl_secure_boot.h>
 591
 592 #endif  /* __CONFIG_H */