2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * Corenet DS style board configuration file
29 #include "../board/freescale/common/ics307_clk.h"
31 /* High Level Configuration Options */
33 #define CONFIG_E500 /* BOOKE e500 family */
34 #define CONFIG_E500MC /* BOOKE e500mc family */
35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
36 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
37 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
38 #define CONFIG_MP /* support multiple processors */
40 #ifndef CONFIG_SYS_TEXT_BASE
41 #define CONFIG_SYS_TEXT_BASE 0xeff80000
44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
45 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
46 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
47 #define CONFIG_PCI /* Enable PCI/PCIE */
48 #define CONFIG_PCIE1 /* PCIE controler 1 */
49 #define CONFIG_PCIE2 /* PCIE controler 2 */
50 #define CONFIG_PCIE3 /* PCIE controler 3 */
51 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
52 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
53 #define CONFIG_SYS_HAS_SERDES /* has SERDES */
55 #define CONFIG_SRIO1 /* SRIO port 1 */
56 #define CONFIG_SRIO2 /* SRIO port 2 */
58 #define CONFIG_FSL_LAW /* Use common FSL init code */
60 #define CONFIG_ENV_OVERWRITE
62 #ifdef CONFIG_SYS_NO_FLASH
63 #define CONFIG_ENV_IS_NOWHERE
65 #define CONFIG_ENV_IS_IN_FLASH
66 #define CONFIG_FLASH_CFI_DRIVER
67 #define CONFIG_SYS_FLASH_CFI
70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
71 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
74 * These can be toggled for performance analysis, otherwise use default.
76 #define CONFIG_SYS_CACHE_STASHING
77 #define CONFIG_BACKSIDE_L2_CACHE
78 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
79 #define CONFIG_BTB /* toggle branch predition */
80 /*#define CONFIG_DDR_ECC*/
82 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
83 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
86 #define CONFIG_ENABLE_36BIT_PHYS
88 #ifdef CONFIG_PHYS_64BIT
89 #define CONFIG_ADDR_MAP
90 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
93 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
94 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
95 #define CONFIG_SYS_MEMTEST_END 0x00400000
96 #define CONFIG_SYS_ALT_MEMTEST
97 #define CONFIG_PANIC_HANG /* do not reset board on panic */
100 * Base addresses -- Note these are effective addresses where the
101 * actual resources get mapped (not physical addresses)
103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */
104 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */
105 #ifdef CONFIG_PHYS_64BIT
106 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */
108 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
110 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
112 #ifdef CONFIG_PHYS_64BIT
113 #define CONFIG_SYS_DCSRBAR 0xf0000000
114 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
118 #define CONFIG_ID_EEPROM
119 #define CONFIG_SYS_I2C_EEPROM_NXID
120 #define CONFIG_SYS_EEPROM_BUS_NUM 0
121 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
122 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
127 #define CONFIG_VERY_BIG_RAM
128 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
129 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
131 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
132 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
134 #define CONFIG_DDR_SPD
135 #define CONFIG_FSL_DDR3
137 #define CONFIG_SYS_SPD_BUS_NUM 1
138 #define SPD_EEPROM_ADDRESS1 0x51
139 #define SPD_EEPROM_ADDRESS2 0x52
140 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
143 * Local Bus Definitions
146 /* Set the local bus clock 1/8 of platform clock */
147 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
149 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
150 #ifdef CONFIG_PHYS_64BIT
151 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
153 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
156 #define CONFIG_SYS_BR0_PRELIM \
157 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
159 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
160 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
162 #define CONFIG_SYS_BR1_PRELIM \
163 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
164 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
166 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
167 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
168 #ifdef CONFIG_PHYS_64BIT
169 #define PIXIS_BASE_PHYS 0xfffdf0000ull
171 #define PIXIS_BASE_PHYS PIXIS_BASE
174 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
175 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
177 #define PIXIS_LBMAP_SWITCH 7
178 #define PIXIS_LBMAP_MASK 0xf0
179 #define PIXIS_LBMAP_SHIFT 4
180 #define PIXIS_LBMAP_ALTBANK 0x40
182 #define CONFIG_SYS_FLASH_QUIET_TEST
183 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
185 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
186 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
187 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
192 #define CONFIG_SYS_FLASH_EMPTY_INFO
193 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
194 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
196 #define CONFIG_BOARD_EARLY_INIT_F
197 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
198 #define CONFIG_MISC_INIT_R
200 #define CONFIG_HWCONFIG
202 /* define to use L1 as initial stack */
203 #define CONFIG_L1_INIT_RAM
204 #define CONFIG_SYS_INIT_RAM_LOCK
205 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
206 #ifdef CONFIG_PHYS_64BIT
207 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
208 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
209 /* The assembler doesn't like typecast */
210 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
211 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
212 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
214 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
215 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
216 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
218 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
220 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
221 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
223 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
224 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
226 /* Serial Port - controlled on board with jumper J8
230 #define CONFIG_CONS_INDEX 1
231 #define CONFIG_SYS_NS16550
232 #define CONFIG_SYS_NS16550_SERIAL
233 #define CONFIG_SYS_NS16550_REG_SIZE 1
234 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
236 #define CONFIG_SYS_BAUDRATE_TABLE \
237 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
239 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
240 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
241 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
242 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
244 /* Use the HUSH parser */
245 #define CONFIG_SYS_HUSH_PARSER
246 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
248 /* pass open firmware flat tree */
249 #define CONFIG_OF_LIBFDT
250 #define CONFIG_OF_BOARD_SETUP
251 #define CONFIG_OF_STDOUT_VIA_ALIAS
253 /* new uImage format support */
255 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
258 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
259 #define CONFIG_HARD_I2C /* I2C with hardware support */
260 #define CONFIG_I2C_MULTI_BUS
261 #define CONFIG_I2C_CMD_TREE
262 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
263 #define CONFIG_SYS_I2C_SLAVE 0x7F
264 #define CONFIG_SYS_I2C_OFFSET 0x118000
265 #define CONFIG_SYS_I2C2_OFFSET 0x118100
270 #define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000
271 #ifdef CONFIG_PHYS_64BIT
272 #define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull
274 #define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000
276 #define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */
278 #define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000
279 #ifdef CONFIG_PHYS_64BIT
280 #define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull
282 #define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000
284 #define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */
288 * Memory space is mapped 1-1, but I/O space must start from 0.
291 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
292 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
293 #ifdef CONFIG_PHYS_64BIT
294 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
295 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
297 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
298 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
300 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
301 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
302 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
303 #ifdef CONFIG_PHYS_64BIT
304 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
306 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
308 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
310 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
311 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
312 #ifdef CONFIG_PHYS_64BIT
313 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
314 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
316 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
317 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
319 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
320 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
321 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
322 #ifdef CONFIG_PHYS_64BIT
323 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
325 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
327 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
329 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
330 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000
331 #ifdef CONFIG_PHYS_64BIT
332 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
333 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
335 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
336 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
338 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
339 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
340 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
341 #ifdef CONFIG_PHYS_64BIT
342 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
344 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
346 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
348 /* controller 4, Base address 203000 */
349 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
350 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
351 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
352 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
353 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
354 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
357 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
358 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
359 #ifdef CONFIG_PHYS_64BIT
360 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
362 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
364 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
365 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
366 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
367 #ifdef CONFIG_PHYS_64BIT
368 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
370 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
372 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
374 #define CONFIG_SYS_DPAA_FMAN
375 #define CONFIG_SYS_DPAA_PME
376 /* Default address of microcode for the Linux Fman driver */
377 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
378 #ifdef CONFIG_PHYS_64BIT
379 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL
381 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR
384 #ifdef CONFIG_SYS_DPAA_FMAN
385 #define CONFIG_FMAN_ENET
390 /*PCIE video card used*/
391 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
397 #define CONFIG_BIOSEMU
398 #define CONFIG_CFB_CONSOLE
399 #define CONFIG_VIDEO_SW_CURSOR
400 #define CONFIG_VGA_AS_SINGLE_DEVICE
401 #define CONFIG_ATI_RADEON_FB
402 #define CONFIG_VIDEO_LOGO
403 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
406 #define CONFIG_NET_MULTI
407 #define CONFIG_PCI_PNP /* do pci plug-and-play */
410 #ifndef CONFIG_PCI_PNP
411 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
412 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
413 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
416 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
417 #define CONFIG_DOS_PARTITION
418 #endif /* CONFIG_PCI */
421 #ifdef CONFIG_FSL_SATA_V2
422 #define CONFIG_LIBATA
423 #define CONFIG_FSL_SATA
425 #define CONFIG_SYS_SATA_MAX_DEVICE 2
427 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
428 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
430 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
431 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
434 #define CONFIG_CMD_SATA
435 #define CONFIG_DOS_PARTITION
436 #define CONFIG_CMD_EXT2
439 #ifdef CONFIG_FMAN_ENET
440 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
441 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
442 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
443 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
444 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
446 #if (CONFIG_SYS_NUM_FMAN == 2)
447 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
448 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
449 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
450 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
451 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
454 #define CONFIG_SYS_TBIPA_VALUE 8
455 #define CONFIG_MII /* MII PHY management */
456 #define CONFIG_ETHPRIME "FM1@DTSEC1"
457 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
463 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
464 #define CONFIG_ENV_SIZE 0x2000
465 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
467 #define CONFIG_LOADS_ECHO /* echo on for serial download */
468 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
471 * Command line configuration.
473 #include <config_cmd_default.h>
475 #define CONFIG_CMD_ELF
476 #define CONFIG_CMD_ERRATA
477 #define CONFIG_CMD_IRQ
478 #define CONFIG_CMD_I2C
479 #define CONFIG_CMD_MII
480 #define CONFIG_CMD_PING
481 #define CONFIG_CMD_SETEXPR
482 #define CONFIG_CMD_DHCP
485 #define CONFIG_CMD_PCI
486 #define CONFIG_CMD_NET
492 #define CONFIG_CMD_USB
493 #define CONFIG_USB_STORAGE
494 #define CONFIG_USB_EHCI
495 #define CONFIG_USB_EHCI_FSL
496 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
497 #define CONFIG_CMD_EXT2
502 #define CONFIG_FSL_ESDHC
503 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
504 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
505 #define CONFIG_CMD_MMC
506 #define CONFIG_GENERIC_MMC
507 #define CONFIG_CMD_EXT2
508 #define CONFIG_CMD_FAT
509 #define CONFIG_DOS_PARTITION
513 * Miscellaneous configurable options
515 #define CONFIG_SYS_LONGHELP /* undef to save memory */
516 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
517 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
518 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
519 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
520 #ifdef CONFIG_CMD_KGDB
521 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
523 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
525 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
526 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
527 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
528 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
531 * For booting Linux, the board info and command line data
532 * have to be in the first 16 MB of memory, since this is
533 * the maximum mapped by the Linux kernel during initialization.
535 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
537 #ifdef CONFIG_CMD_KGDB
538 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
539 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
543 * Environment Configuration
545 #define CONFIG_ROOTPATH /opt/nfsroot
546 #define CONFIG_BOOTFILE uImage
547 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
549 /* default location for tftp and bootm */
550 #define CONFIG_LOADADDR 1000000
552 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
554 #define CONFIG_BAUDRATE 115200
556 #define CONFIG_EXTRA_ENV_SETTINGS \
557 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
558 "bank_intlv=cs0_cs1\0" \
560 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
561 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
562 "tftpflash=tftpboot $loadaddr $uboot && " \
563 "protect off $ubootaddr +$filesize && " \
564 "erase $ubootaddr +$filesize && " \
565 "cp.b $loadaddr $ubootaddr $filesize && " \
566 "protect on $ubootaddr +$filesize && " \
567 "cmp.b $loadaddr $ubootaddr $filesize\0" \
568 "consoledev=ttyS0\0" \
569 "ramdiskaddr=2000000\0" \
570 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
572 "fdtfile=p4080ds/p4080ds.dtb\0" \
575 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0"
577 #define CONFIG_HDBOOT \
578 "setenv bootargs root=/dev/$bdev rw " \
579 "console=$consoledev,$baudrate $othbootargs;" \
580 "tftp $loadaddr $bootfile;" \
581 "tftp $fdtaddr $fdtfile;" \
582 "bootm $loadaddr - $fdtaddr"
584 #define CONFIG_NFSBOOTCOMMAND \
585 "setenv bootargs root=/dev/nfs rw " \
586 "nfsroot=$serverip:$rootpath " \
587 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
588 "console=$consoledev,$baudrate $othbootargs;" \
589 "tftp $loadaddr $bootfile;" \
590 "tftp $fdtaddr $fdtfile;" \
591 "bootm $loadaddr - $fdtaddr"
593 #define CONFIG_RAMBOOTCOMMAND \
594 "setenv bootargs root=/dev/ram rw " \
595 "console=$consoledev,$baudrate $othbootargs;" \
596 "tftp $ramdiskaddr $ramdiskfile;" \
597 "tftp $loadaddr $bootfile;" \
598 "tftp $fdtaddr $fdtfile;" \
599 "bootm $loadaddr $ramdiskaddr $fdtaddr"
601 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
603 #endif /* __CONFIG_H */