include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  19 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  20 #endif
  21
  22 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  23 /* Set 1M boot space */
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  26                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  28 #endif
  29
  30 /* High Level Configuration Options */
  31
  32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  34 #endif
  35
  36 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  37
  38 /*
  39  * These can be toggled for performance analysis, otherwise use default.
  40  */
  41 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  42 #ifdef CONFIG_DDR_ECC
  43 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  44 #endif
  45
  46 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  47
  48 /*
  49  *  Config the L3 Cache as L3 SRAM
  50  */
  51 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  52 #ifdef CONFIG_PHYS_64BIT
  53 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  54 #else
  55 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  56 #endif
  57 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  58 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  59
  60 #ifdef CONFIG_PHYS_64BIT
  61 #define CONFIG_SYS_DCSRBAR              0xf0000000
  62 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  63 #endif
  64
  65 /* EEPROM */
  66 #define CONFIG_SYS_I2C_EEPROM_NXID
  67 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  68
  69 /*
  70  * DDR Setup
  71  */
  72 #define CONFIG_VERY_BIG_RAM
  73 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  74 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  75
  76 #define SPD_EEPROM_ADDRESS1     0x51
  77 #define SPD_EEPROM_ADDRESS2     0x52
  78 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
  79 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  80
  81 /*
  82  * Local Bus Definitions
  83  */
  84
  85 /* Set the local bus clock 1/8 of platform clock */
  86 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  87
  88 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
  89 #ifdef CONFIG_PHYS_64BIT
  90 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
  91 #else
  92 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  93 #endif
  94
  95 #define CONFIG_SYS_FLASH_BR_PRELIM \
  96                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
  97                  | BR_PS_16 | BR_V)
  98 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
  99                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 100
 101 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 102 #ifdef CONFIG_PHYS_64BIT
 103 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 104 #else
 105 #define PIXIS_BASE_PHYS         PIXIS_BASE
 106 #endif
 107
 108 #define PIXIS_LBMAP_SWITCH      7
 109 #define PIXIS_LBMAP_MASK        0xf0
 110 #define PIXIS_LBMAP_SHIFT       4
 111 #define PIXIS_LBMAP_ALTBANK     0x40
 112
 113 #define CONFIG_SYS_FLASH_QUIET_TEST
 114 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 115
 116 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 117
 118 /* Nand Flash */
 119 #ifdef CONFIG_NAND_FSL_ELBC
 120 #define CONFIG_SYS_NAND_BASE            0xffa00000
 121 #ifdef CONFIG_PHYS_64BIT
 122 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 123 #else
 124 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 125 #endif
 126
 127 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 128 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 129
 130 /* NAND flash config */
 131 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 132                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 133                                | BR_PS_8               /* Port Size = 8 bit */ \
 134                                | BR_MS_FCM             /* MSEL = FCM */ \
 135                                | BR_V)                 /* valid */
 136 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 137                                | OR_FCM_PGS            /* Large Page*/ \
 138                                | OR_FCM_CSCT \
 139                                | OR_FCM_CST \
 140                                | OR_FCM_CHT \
 141                                | OR_FCM_SCY_1 \
 142                                | OR_FCM_TRLX \
 143                                | OR_FCM_EHTR)
 144 #endif /* CONFIG_NAND_FSL_ELBC */
 145
 146 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 147
 148 #define CONFIG_HWCONFIG
 149
 150 /* define to use L1 as initial stack */
 151 #define CONFIG_L1_INIT_RAM
 152 #define CONFIG_SYS_INIT_RAM_LOCK
 153 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 154 #ifdef CONFIG_PHYS_64BIT
 155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 156 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 157 /* The assembler doesn't like typecast */
 158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 159         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 160           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 161 #else
 162 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 163 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 164 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 165 #endif
 166 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 167
 168 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 169
 170 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 171
 172 /* Serial Port - controlled on board with jumper J8
 173  * open - index 2
 174  * shorted - index 1
 175  */
 176 #define CONFIG_SYS_NS16550_SERIAL
 177 #define CONFIG_SYS_NS16550_REG_SIZE     1
 178 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 179
 180 #define CONFIG_SYS_BAUDRATE_TABLE       \
 181         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 182
 183 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 184 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 185 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 186 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 187
 188 /* I2C */
 189
 190 /*
 191  * RapidIO
 192  */
 193 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 194 #ifdef CONFIG_PHYS_64BIT
 195 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 196 #else
 197 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 198 #endif
 199 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 200
 201 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 202 #ifdef CONFIG_PHYS_64BIT
 203 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 204 #else
 205 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 206 #endif
 207 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 208
 209 /*
 210  * for slave u-boot IMAGE instored in master memory space,
 211  * PHYS must be aligned based on the SIZE
 212  */
 213 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 214 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 215 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 216 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 217 /*
 218  * for slave UCODE and ENV instored in master memory space,
 219  * PHYS must be aligned based on the SIZE
 220  */
 221 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 222 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 223 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 224
 225 /* slave core release by master*/
 226 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 227 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 228
 229 /*
 230  * SRIO_PCIE_BOOT - SLAVE
 231  */
 232 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 233 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 234 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 235                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 236 #endif
 237
 238 /*
 239  * eSPI - Enhanced SPI
 240  */
 241
 242 /*
 243  * General PCI
 244  * Memory space is mapped 1-1, but I/O space must start from 0.
 245  */
 246
 247 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 248 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 249 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 250 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 251 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 252
 253 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 254 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 255 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 256 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 257 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 258
 259 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 260 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 261 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 262 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 263 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 264
 265 /* controller 4, Base address 203000 */
 266 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 267 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 268
 269 /* Qman/Bman */
 270 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 271 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 272 #ifdef CONFIG_PHYS_64BIT
 273 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 274 #else
 275 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 276 #endif
 277 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 278 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 279 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 280 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 281 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 282 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 283                                         CONFIG_SYS_BMAN_CENA_SIZE)
 284 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 285 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 286 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 287 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 288 #ifdef CONFIG_PHYS_64BIT
 289 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 290 #else
 291 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 292 #endif
 293 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 294 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 295 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 296 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 297 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 298 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 299                                         CONFIG_SYS_QMAN_CENA_SIZE)
 300 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 301 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 302
 303 #define CONFIG_SYS_DPAA_FMAN
 304 #define CONFIG_SYS_DPAA_PME
 305 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 306
 307 #ifdef CONFIG_FMAN_ENET
 308 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 309 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 310 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 311 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 312 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 313
 314 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 315 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 316 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 317 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 318 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 319
 320 #define CONFIG_SYS_TBIPA_VALUE  8
 321 #endif
 322
 323 /*
 324  * Environment
 325  */
 326 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 327 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 328
 329 #ifdef CONFIG_MMC
 330 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 331 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 332 #endif
 333
 334 /*
 335  * Miscellaneous configurable options
 336  */
 337
 338 /*
 339  * For booting Linux, the board info and command line data
 340  * have to be in the first 64 MB of memory, since this is
 341  * the maximum mapped by the Linux kernel during initialization.
 342  */
 343 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 344
 345 /*
 346  * Environment Configuration
 347  */
 348 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 349 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 350
 351 #ifdef CONFIG_TARGET_P4080DS
 352 #define __USB_PHY_TYPE  ulpi
 353 #else
 354 #define __USB_PHY_TYPE  utmi
 355 #endif
 356
 357 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 358         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 359         "bank_intlv=cs0_cs1;"                                   \
 360         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 361         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 362         "netdev=eth0\0"                                         \
 363         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 364         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 365         "tftpflash=tftpboot $loadaddr $uboot && "               \
 366         "protect off $ubootaddr +$filesize && "                 \
 367         "erase $ubootaddr +$filesize && "                       \
 368         "cp.b $loadaddr $ubootaddr $filesize && "               \
 369         "protect on $ubootaddr +$filesize && "                  \
 370         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 371         "consoledev=ttyS0\0"                                    \
 372         "ramdiskaddr=2000000\0"                                 \
 373         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 374         "fdtaddr=1e00000\0"                                     \
 375         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 376         "bdev=sda3\0"
 377
 378 #include <asm/fsl_secure_boot.h>
 379
 380 #endif  /* __CONFIG_H */