include/configs/corenet_ds.h

   1 /*
   2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include "../board/freescale/common/ics307_clk.h"
  14
  15 #ifdef CONFIG_RAMBOOT_PBL
  16 #ifdef CONFIG_SECURE_BOOT
  17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  19 #ifdef CONFIG_NAND
  20 #define CONFIG_RAMBOOT_NAND
  21 #endif
  22 #define CONFIG_BOOTSCRIPT_COPY_RAM
  23 #else
  24 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  25 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  27 #if defined(CONFIG_TARGET_P3041DS)
  28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  29 #elif defined(CONFIG_TARGET_P4080DS)
  30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  31 #elif defined(CONFIG_TARGET_P5020DS)
  32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  33 #elif defined(CONFIG_TARGET_P5040DS)
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  35 #endif
  36 #endif
  37 #endif
  38
  39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  40 /* Set 1M boot space */
  41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  43                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  45 #endif
  46
  47 /* High Level Configuration Options */
  48 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  49 #define CONFIG_MP                       /* support multiple processors */
  50
  51 #ifndef CONFIG_SYS_TEXT_BASE
  52 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  53 #endif
  54
  55 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  56 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  57 #endif
  58
  59 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  60 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  61 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  62 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  63 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  64 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  65 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  66
  67 #define CONFIG_ENV_OVERWRITE
  68
  69 #ifndef CONFIG_MTD_NOR_FLASH
  70 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  71 #define CONFIG_ENV_IS_NOWHERE
  72 #endif
  73 #else
  74 #define CONFIG_FLASH_CFI_DRIVER
  75 #define CONFIG_SYS_FLASH_CFI
  76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  77 #endif
  78
  79 #if defined(CONFIG_SPIFLASH)
  80 #define CONFIG_SYS_EXTRA_ENV_RELOC
  81 #define CONFIG_ENV_IS_IN_SPI_FLASH
  82 #define CONFIG_ENV_SPI_BUS              0
  83 #define CONFIG_ENV_SPI_CS               0
  84 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  85 #define CONFIG_ENV_SPI_MODE             0
  86 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  87 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  88 #define CONFIG_ENV_SECT_SIZE            0x10000
  89 #elif defined(CONFIG_SDCARD)
  90 #define CONFIG_SYS_EXTRA_ENV_RELOC
  91 #define CONFIG_ENV_IS_IN_MMC
  92 #define CONFIG_FSL_FIXED_MMC_LOCATION
  93 #define CONFIG_SYS_MMC_ENV_DEV          0
  94 #define CONFIG_ENV_SIZE                 0x2000
  95 #define CONFIG_ENV_OFFSET               (512 * 1658)
  96 #elif defined(CONFIG_NAND)
  97 #define CONFIG_SYS_EXTRA_ENV_RELOC
  98 #define CONFIG_ENV_IS_IN_NAND
  99 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 100 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 101 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 102 #define CONFIG_ENV_IS_IN_REMOTE
 103 #define CONFIG_ENV_ADDR         0xffe20000
 104 #define CONFIG_ENV_SIZE         0x2000
 105 #elif defined(CONFIG_ENV_IS_NOWHERE)
 106 #define CONFIG_ENV_SIZE         0x2000
 107 #else
 108 #define CONFIG_ENV_IS_IN_FLASH
 109 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 110 #define CONFIG_ENV_SIZE         0x2000
 111 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 112 #endif
 113
 114 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 115
 116 /*
 117  * These can be toggled for performance analysis, otherwise use default.
 118  */
 119 #define CONFIG_SYS_CACHE_STASHING
 120 #define CONFIG_BACKSIDE_L2_CACHE
 121 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 122 #define CONFIG_BTB                      /* toggle branch predition */
 123 #define CONFIG_DDR_ECC
 124 #ifdef CONFIG_DDR_ECC
 125 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 126 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 127 #endif
 128
 129 #define CONFIG_ENABLE_36BIT_PHYS
 130
 131 #ifdef CONFIG_PHYS_64BIT
 132 #define CONFIG_ADDR_MAP
 133 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 134 #endif
 135
 136 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 137 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 138 #define CONFIG_SYS_MEMTEST_END          0x00400000
 139 #define CONFIG_SYS_ALT_MEMTEST
 140 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 141
 142 /*
 143  *  Config the L3 Cache as L3 SRAM
 144  */
 145 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 146 #ifdef CONFIG_PHYS_64BIT
 147 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 148 #else
 149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 150 #endif
 151 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 152 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 153
 154 #ifdef CONFIG_PHYS_64BIT
 155 #define CONFIG_SYS_DCSRBAR              0xf0000000
 156 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 157 #endif
 158
 159 /* EEPROM */
 160 #define CONFIG_ID_EEPROM
 161 #define CONFIG_SYS_I2C_EEPROM_NXID
 162 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 163 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 164 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 165
 166 /*
 167  * DDR Setup
 168  */
 169 #define CONFIG_VERY_BIG_RAM
 170 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 171 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 172
 173 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 174 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 175
 176 #define CONFIG_DDR_SPD
 177
 178 #define CONFIG_SYS_SPD_BUS_NUM  1
 179 #define SPD_EEPROM_ADDRESS1     0x51
 180 #define SPD_EEPROM_ADDRESS2     0x52
 181 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 182 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 183
 184 /*
 185  * Local Bus Definitions
 186  */
 187
 188 /* Set the local bus clock 1/8 of platform clock */
 189 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 190
 191 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 192 #ifdef CONFIG_PHYS_64BIT
 193 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 194 #else
 195 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 196 #endif
 197
 198 #define CONFIG_SYS_FLASH_BR_PRELIM \
 199                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 200                  | BR_PS_16 | BR_V)
 201 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 202                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 203
 204 #define CONFIG_SYS_BR1_PRELIM \
 205         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 206 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 207
 208 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 209 #ifdef CONFIG_PHYS_64BIT
 210 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 211 #else
 212 #define PIXIS_BASE_PHYS         PIXIS_BASE
 213 #endif
 214
 215 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 216 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 217
 218 #define PIXIS_LBMAP_SWITCH      7
 219 #define PIXIS_LBMAP_MASK        0xf0
 220 #define PIXIS_LBMAP_SHIFT       4
 221 #define PIXIS_LBMAP_ALTBANK     0x40
 222
 223 #define CONFIG_SYS_FLASH_QUIET_TEST
 224 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 225
 226 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 227 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 228 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 229 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 230
 231 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 232
 233 #if defined(CONFIG_RAMBOOT_PBL)
 234 #define CONFIG_SYS_RAMBOOT
 235 #endif
 236
 237 /* Nand Flash */
 238 #ifdef CONFIG_NAND_FSL_ELBC
 239 #define CONFIG_SYS_NAND_BASE            0xffa00000
 240 #ifdef CONFIG_PHYS_64BIT
 241 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 242 #else
 243 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 244 #endif
 245
 246 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 247 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 248 #define CONFIG_CMD_NAND
 249 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 250
 251 /* NAND flash config */
 252 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 253                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 254                                | BR_PS_8               /* Port Size = 8 bit */ \
 255                                | BR_MS_FCM             /* MSEL = FCM */ \
 256                                | BR_V)                 /* valid */
 257 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 258                                | OR_FCM_PGS            /* Large Page*/ \
 259                                | OR_FCM_CSCT \
 260                                | OR_FCM_CST \
 261                                | OR_FCM_CHT \
 262                                | OR_FCM_SCY_1 \
 263                                | OR_FCM_TRLX \
 264                                | OR_FCM_EHTR)
 265
 266 #ifdef CONFIG_NAND
 267 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 268 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 269 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 270 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 271 #else
 272 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 273 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 274 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 275 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 276 #endif
 277 #else
 278 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 279 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 280 #endif /* CONFIG_NAND_FSL_ELBC */
 281
 282 #define CONFIG_SYS_FLASH_EMPTY_INFO
 283 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 284 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 285
 286 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 287 #define CONFIG_MISC_INIT_R
 288
 289 #define CONFIG_HWCONFIG
 290
 291 /* define to use L1 as initial stack */
 292 #define CONFIG_L1_INIT_RAM
 293 #define CONFIG_SYS_INIT_RAM_LOCK
 294 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 295 #ifdef CONFIG_PHYS_64BIT
 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 298 /* The assembler doesn't like typecast */
 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 300         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 301           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 302 #else
 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 306 #endif
 307 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 308
 309 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 310 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 311
 312 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 313 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 314
 315 /* Serial Port - controlled on board with jumper J8
 316  * open - index 2
 317  * shorted - index 1
 318  */
 319 #define CONFIG_CONS_INDEX       1
 320 #define CONFIG_SYS_NS16550_SERIAL
 321 #define CONFIG_SYS_NS16550_REG_SIZE     1
 322 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 323
 324 #define CONFIG_SYS_BAUDRATE_TABLE       \
 325         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 326
 327 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 328 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 329 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 330 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 331
 332 /* I2C */
 333 #define CONFIG_SYS_I2C
 334 #define CONFIG_SYS_I2C_FSL
 335 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 336 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 337 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 338 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 339 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 340 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 341
 342 /*
 343  * RapidIO
 344  */
 345 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 346 #ifdef CONFIG_PHYS_64BIT
 347 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 348 #else
 349 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 350 #endif
 351 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 352
 353 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 354 #ifdef CONFIG_PHYS_64BIT
 355 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 356 #else
 357 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 358 #endif
 359 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 360
 361 /*
 362  * for slave u-boot IMAGE instored in master memory space,
 363  * PHYS must be aligned based on the SIZE
 364  */
 365 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 366 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 369 /*
 370  * for slave UCODE and ENV instored in master memory space,
 371  * PHYS must be aligned based on the SIZE
 372  */
 373 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 374 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 375 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 376
 377 /* slave core release by master*/
 378 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 379 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 380
 381 /*
 382  * SRIO_PCIE_BOOT - SLAVE
 383  */
 384 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 385 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 386 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 387                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 388 #endif
 389
 390 /*
 391  * eSPI - Enhanced SPI
 392  */
 393 #define CONFIG_SF_DEFAULT_SPEED         10000000
 394 #define CONFIG_SF_DEFAULT_MODE          0
 395
 396 /*
 397  * General PCI
 398  * Memory space is mapped 1-1, but I/O space must start from 0.
 399  */
 400
 401 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 402 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 403 #ifdef CONFIG_PHYS_64BIT
 404 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 405 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 406 #else
 407 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 408 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 409 #endif
 410 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 411 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 412 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 413 #ifdef CONFIG_PHYS_64BIT
 414 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 415 #else
 416 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 417 #endif
 418 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 419
 420 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 421 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 422 #ifdef CONFIG_PHYS_64BIT
 423 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 424 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 425 #else
 426 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 427 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 428 #endif
 429 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 430 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 431 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 432 #ifdef CONFIG_PHYS_64BIT
 433 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 434 #else
 435 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 436 #endif
 437 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 438
 439 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 440 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 441 #ifdef CONFIG_PHYS_64BIT
 442 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 443 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 444 #else
 445 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 446 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 447 #endif
 448 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 449 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 450 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 451 #ifdef CONFIG_PHYS_64BIT
 452 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 453 #else
 454 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 455 #endif
 456 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 457
 458 /* controller 4, Base address 203000 */
 459 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 460 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 461 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 462 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 463 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 464 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 465
 466 /* Qman/Bman */
 467 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 468 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 469 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 470 #ifdef CONFIG_PHYS_64BIT
 471 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 472 #else
 473 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 474 #endif
 475 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 476 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 477 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 478 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 479 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 480 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 481                                         CONFIG_SYS_BMAN_CENA_SIZE)
 482 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 483 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 484 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 485 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 486 #ifdef CONFIG_PHYS_64BIT
 487 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 488 #else
 489 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 490 #endif
 491 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 492 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 493 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 494 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 495 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 496 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 497                                         CONFIG_SYS_QMAN_CENA_SIZE)
 498 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 499 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 500
 501 #define CONFIG_SYS_DPAA_FMAN
 502 #define CONFIG_SYS_DPAA_PME
 503 /* Default address of microcode for the Linux Fman driver */
 504 #if defined(CONFIG_SPIFLASH)
 505 /*
 506  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 507  * env, so we got 0x110000.
 508  */
 509 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 510 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 511 #elif defined(CONFIG_SDCARD)
 512 /*
 513  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 514  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 515  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 516  */
 517 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 518 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 519 #elif defined(CONFIG_NAND)
 520 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 521 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 522 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 523 /*
 524  * Slave has no ucode locally, it can fetch this from remote. When implementing
 525  * in two corenet boards, slave's ucode could be stored in master's memory
 526  * space, the address can be mapped from slave TLB->slave LAW->
 527  * slave SRIO or PCIE outbound window->master inbound window->
 528  * master LAW->the ucode address in master's memory space.
 529  */
 530 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 531 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 532 #else
 533 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 534 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 535 #endif
 536 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 537 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 538
 539 #ifdef CONFIG_SYS_DPAA_FMAN
 540 #define CONFIG_FMAN_ENET
 541 #define CONFIG_PHYLIB_10G
 542 #define CONFIG_PHY_VITESSE
 543 #define CONFIG_PHY_TERANETICS
 544 #endif
 545
 546 #ifdef CONFIG_PCI
 547 #define CONFIG_PCI_INDIRECT_BRIDGE
 548
 549 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 550 #endif  /* CONFIG_PCI */
 551
 552 /* SATA */
 553 #ifdef CONFIG_FSL_SATA_V2
 554 #define CONFIG_LIBATA
 555 #define CONFIG_FSL_SATA
 556
 557 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 558 #define CONFIG_SATA1
 559 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 560 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 561 #define CONFIG_SATA2
 562 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 563 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 564
 565 #define CONFIG_LBA48
 566 #define CONFIG_CMD_SATA
 567 #endif
 568
 569 #ifdef CONFIG_FMAN_ENET
 570 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 571 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 572 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 573 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 574 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 575
 576 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 577 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 578 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 579 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 580 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 581
 582 #define CONFIG_SYS_TBIPA_VALUE  8
 583 #define CONFIG_MII              /* MII PHY management */
 584 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 585 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 586 #endif
 587
 588 /*
 589  * Environment
 590  */
 591 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 592 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 593
 594 /*
 595  * Command line configuration.
 596  */
 597 #define CONFIG_CMD_ERRATA
 598 #define CONFIG_CMD_IRQ
 599 #define CONFIG_CMD_REGINFO
 600
 601 #ifdef CONFIG_PCI
 602 #define CONFIG_CMD_PCI
 603 #endif
 604
 605 /*
 606 * USB
 607 */
 608 #define CONFIG_HAS_FSL_DR_USB
 609 #define CONFIG_HAS_FSL_MPH_USB
 610
 611 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 612 #define CONFIG_USB_EHCI
 613 #define CONFIG_USB_EHCI_FSL
 614 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 615 #endif
 616
 617 #ifdef CONFIG_MMC
 618 #define CONFIG_FSL_ESDHC
 619 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 620 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 621 #endif
 622
 623 /* Hash command with SHA acceleration supported in hardware */
 624 #ifdef CONFIG_FSL_CAAM
 625 #define CONFIG_CMD_HASH
 626 #define CONFIG_SHA_HW_ACCEL
 627 #endif
 628
 629 /*
 630  * Miscellaneous configurable options
 631  */
 632 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 633 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 634 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 635 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 636 #ifdef CONFIG_CMD_KGDB
 637 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 638 #else
 639 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 640 #endif
 641 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 642 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 643 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 644
 645 /*
 646  * For booting Linux, the board info and command line data
 647  * have to be in the first 64 MB of memory, since this is
 648  * the maximum mapped by the Linux kernel during initialization.
 649  */
 650 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 651 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 652
 653 #ifdef CONFIG_CMD_KGDB
 654 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 655 #endif
 656
 657 /*
 658  * Environment Configuration
 659  */
 660 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 661 #define CONFIG_BOOTFILE         "uImage"
 662 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 663
 664 /* default location for tftp and bootm */
 665 #define CONFIG_LOADADDR         1000000
 666
 667
 668 #define CONFIG_BAUDRATE 115200
 669
 670 #ifdef CONFIG_TARGET_P4080DS
 671 #define __USB_PHY_TYPE  ulpi
 672 #else
 673 #define __USB_PHY_TYPE  utmi
 674 #endif
 675
 676 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 677         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 678         "bank_intlv=cs0_cs1;"                                   \
 679         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 680         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 681         "netdev=eth0\0"                                         \
 682         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 683         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 684         "tftpflash=tftpboot $loadaddr $uboot && "               \
 685         "protect off $ubootaddr +$filesize && "                 \
 686         "erase $ubootaddr +$filesize && "                       \
 687         "cp.b $loadaddr $ubootaddr $filesize && "               \
 688         "protect on $ubootaddr +$filesize && "                  \
 689         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 690         "consoledev=ttyS0\0"                                    \
 691         "ramdiskaddr=2000000\0"                                 \
 692         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 693         "fdtaddr=1e00000\0"                                     \
 694         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 695         "bdev=sda3\0"
 696
 697 #define CONFIG_HDBOOT                                   \
 698         "setenv bootargs root=/dev/$bdev rw "           \
 699         "console=$consoledev,$baudrate $othbootargs;"   \
 700         "tftp $loadaddr $bootfile;"                     \
 701         "tftp $fdtaddr $fdtfile;"                       \
 702         "bootm $loadaddr - $fdtaddr"
 703
 704 #define CONFIG_NFSBOOTCOMMAND                   \
 705         "setenv bootargs root=/dev/nfs rw "     \
 706         "nfsroot=$serverip:$rootpath "          \
 707         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 708         "console=$consoledev,$baudrate $othbootargs;"   \
 709         "tftp $loadaddr $bootfile;"             \
 710         "tftp $fdtaddr $fdtfile;"               \
 711         "bootm $loadaddr - $fdtaddr"
 712
 713 #define CONFIG_RAMBOOTCOMMAND                           \
 714         "setenv bootargs root=/dev/ram rw "             \
 715         "console=$consoledev,$baudrate $othbootargs;"   \
 716         "tftp $ramdiskaddr $ramdiskfile;"               \
 717         "tftp $loadaddr $bootfile;"                     \
 718         "tftp $fdtaddr $fdtfile;"                       \
 719         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 720
 721 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 722
 723 #include <asm/fsl_secure_boot.h>
 724
 725 #endif  /* __CONFIG_H */