1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
19 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
23 /* Set 1M boot space */
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
26 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
30 /* High Level Configuration Options */
32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
36 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
39 * These can be toggled for performance analysis, otherwise use default.
41 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
43 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
46 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
49 * Config the L3 Cache as L3 SRAM
51 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
52 #ifdef CONFIG_PHYS_64BIT
53 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
55 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
57 #define CONFIG_SYS_L3_SIZE (1024 << 10)
58 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
60 #ifdef CONFIG_PHYS_64BIT
61 #define CONFIG_SYS_DCSRBAR 0xf0000000
62 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
66 #define CONFIG_SYS_I2C_EEPROM_NXID
67 #define CONFIG_SYS_EEPROM_BUS_NUM 0
72 #define CONFIG_VERY_BIG_RAM
73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
76 #define SPD_EEPROM_ADDRESS1 0x51
77 #define SPD_EEPROM_ADDRESS2 0x52
78 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
79 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
82 * Local Bus Definitions
85 /* Set the local bus clock 1/8 of platform clock */
86 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
88 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
89 #ifdef CONFIG_PHYS_64BIT
90 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
92 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
95 #define CONFIG_SYS_FLASH_BR_PRELIM \
96 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
98 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
99 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
101 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
102 #ifdef CONFIG_PHYS_64BIT
103 #define PIXIS_BASE_PHYS 0xfffdf0000ull
105 #define PIXIS_BASE_PHYS PIXIS_BASE
108 #define PIXIS_LBMAP_SWITCH 7
109 #define PIXIS_LBMAP_MASK 0xf0
110 #define PIXIS_LBMAP_SHIFT 4
111 #define PIXIS_LBMAP_ALTBANK 0x40
113 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
116 #ifdef CONFIG_NAND_FSL_ELBC
117 #define CONFIG_SYS_NAND_BASE 0xffa00000
118 #ifdef CONFIG_PHYS_64BIT
119 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
121 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
124 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
125 #define CONFIG_SYS_MAX_NAND_DEVICE 1
127 /* NAND flash config */
128 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
129 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
130 | BR_PS_8 /* Port Size = 8 bit */ \
131 | BR_MS_FCM /* MSEL = FCM */ \
133 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
134 | OR_FCM_PGS /* Large Page*/ \
141 #endif /* CONFIG_NAND_FSL_ELBC */
143 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
145 #define CONFIG_HWCONFIG
147 /* define to use L1 as initial stack */
148 #define CONFIG_L1_INIT_RAM
149 #define CONFIG_SYS_INIT_RAM_LOCK
150 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
151 #ifdef CONFIG_PHYS_64BIT
152 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
153 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
154 /* The assembler doesn't like typecast */
155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
156 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
157 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
160 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
161 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
163 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
165 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
167 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
169 /* Serial Port - controlled on board with jumper J8
173 #define CONFIG_SYS_NS16550_SERIAL
174 #define CONFIG_SYS_NS16550_REG_SIZE 1
175 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
177 #define CONFIG_SYS_BAUDRATE_TABLE \
178 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
180 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
181 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
182 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
183 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
190 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
191 #ifdef CONFIG_PHYS_64BIT
192 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
194 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
196 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
198 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
199 #ifdef CONFIG_PHYS_64BIT
200 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
202 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
204 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
207 * for slave u-boot IMAGE instored in master memory space,
208 * PHYS must be aligned based on the SIZE
210 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
211 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
212 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
213 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
215 * for slave UCODE and ENV instored in master memory space,
216 * PHYS must be aligned based on the SIZE
218 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
219 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
220 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
222 /* slave core release by master*/
223 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
224 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
227 * SRIO_PCIE_BOOT - SLAVE
229 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
230 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
231 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
232 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
236 * eSPI - Enhanced SPI
241 * Memory space is mapped 1-1, but I/O space must start from 0.
244 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
245 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
247 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
248 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
250 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
251 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
252 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
253 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
254 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
256 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
257 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
258 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
259 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
260 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
262 /* controller 4, Base address 203000 */
263 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
264 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
267 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
268 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
269 #ifdef CONFIG_PHYS_64BIT
270 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
272 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
274 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
275 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
276 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
277 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
278 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
279 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
280 CONFIG_SYS_BMAN_CENA_SIZE)
281 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
282 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
283 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
284 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
285 #ifdef CONFIG_PHYS_64BIT
286 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
288 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
290 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
291 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
292 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
293 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
294 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
295 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
296 CONFIG_SYS_QMAN_CENA_SIZE)
297 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
298 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
300 #define CONFIG_SYS_DPAA_FMAN
301 #define CONFIG_SYS_DPAA_PME
302 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
304 #ifdef CONFIG_FMAN_ENET
305 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
306 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
307 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
308 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
309 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
311 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
312 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
313 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
314 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
315 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
317 #define CONFIG_SYS_TBIPA_VALUE 8
323 #define CONFIG_LOADS_ECHO /* echo on for serial download */
324 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
327 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
328 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
332 * Miscellaneous configurable options
336 * For booting Linux, the board info and command line data
337 * have to be in the first 64 MB of memory, since this is
338 * the maximum mapped by the Linux kernel during initialization.
340 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
343 * Environment Configuration
345 #define CONFIG_ROOTPATH "/opt/nfsroot"
346 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
348 #ifdef CONFIG_TARGET_P4080DS
349 #define __USB_PHY_TYPE ulpi
351 #define __USB_PHY_TYPE utmi
354 #define CONFIG_EXTRA_ENV_SETTINGS \
355 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
356 "bank_intlv=cs0_cs1;" \
357 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
358 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
360 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
361 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
362 "tftpflash=tftpboot $loadaddr $uboot && " \
363 "protect off $ubootaddr +$filesize && " \
364 "erase $ubootaddr +$filesize && " \
365 "cp.b $loadaddr $ubootaddr $filesize && " \
366 "protect on $ubootaddr +$filesize && " \
367 "cmp.b $loadaddr $ubootaddr $filesize\0" \
368 "consoledev=ttyS0\0" \
369 "ramdiskaddr=2000000\0" \
370 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
371 "fdtaddr=1e00000\0" \
372 "fdtfile=p4080ds/p4080ds.dtb\0" \
375 #include <asm/fsl_secure_boot.h>
377 #endif /* __CONFIG_H */