include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #ifdef CONFIG_NXP_ESBC
  19 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  21 #ifdef CONFIG_MTD_RAW_NAND
  22 #define CONFIG_RAMBOOT_NAND
  23 #endif
  24 #define CONFIG_BOOTSCRIPT_COPY_RAM
  25 #else
  26 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  28 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  29 #if defined(CONFIG_TARGET_P3041DS)
  30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  31 #elif defined(CONFIG_TARGET_P4080DS)
  32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  33 #elif defined(CONFIG_TARGET_P5020DS)
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  35 #elif defined(CONFIG_TARGET_P5040DS)
  36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  37 #endif
  38 #endif
  39 #endif
  40
  41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  42 /* Set 1M boot space */
  43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  45                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  47 #endif
  48
  49 /* High Level Configuration Options */
  50 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  51
  52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  53 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  54 #endif
  55
  56 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  57 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  58 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  59 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  60 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  61
  62 #if defined(CONFIG_SPIFLASH)
  63 #elif defined(CONFIG_SDCARD)
  64 #define CONFIG_FSL_FIXED_MMC_LOCATION
  65 #endif
  66
  67 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_SYS_CACHE_STASHING
  73 #define CONFIG_BACKSIDE_L2_CACHE
  74 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  75 #define CONFIG_BTB                      /* toggle branch predition */
  76 #define CONFIG_DDR_ECC
  77 #ifdef CONFIG_DDR_ECC
  78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  79 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  80 #endif
  81
  82 #define CONFIG_ENABLE_36BIT_PHYS
  83
  84 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  85
  86 /*
  87  *  Config the L3 Cache as L3 SRAM
  88  */
  89 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  90 #ifdef CONFIG_PHYS_64BIT
  91 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  92 #else
  93 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  94 #endif
  95 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  96 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  97
  98 #ifdef CONFIG_PHYS_64BIT
  99 #define CONFIG_SYS_DCSRBAR              0xf0000000
 100 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 101 #endif
 102
 103 /* EEPROM */
 104 #define CONFIG_SYS_I2C_EEPROM_NXID
 105 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 106
 107 /*
 108  * DDR Setup
 109  */
 110 #define CONFIG_VERY_BIG_RAM
 111 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 112 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 113
 114 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 115 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 116
 117 #define CONFIG_DDR_SPD
 118
 119 #define CONFIG_SYS_SPD_BUS_NUM  1
 120 #define SPD_EEPROM_ADDRESS1     0x51
 121 #define SPD_EEPROM_ADDRESS2     0x52
 122 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 123 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 124
 125 /*
 126  * Local Bus Definitions
 127  */
 128
 129 /* Set the local bus clock 1/8 of platform clock */
 130 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 131
 132 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 133 #ifdef CONFIG_PHYS_64BIT
 134 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 135 #else
 136 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 137 #endif
 138
 139 #define CONFIG_SYS_FLASH_BR_PRELIM \
 140                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 141                  | BR_PS_16 | BR_V)
 142 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 143                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 144
 145 #define CONFIG_SYS_BR1_PRELIM \
 146         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 147 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 148
 149 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 150 #ifdef CONFIG_PHYS_64BIT
 151 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 152 #else
 153 #define PIXIS_BASE_PHYS         PIXIS_BASE
 154 #endif
 155
 156 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 157 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 158
 159 #define PIXIS_LBMAP_SWITCH      7
 160 #define PIXIS_LBMAP_MASK        0xf0
 161 #define PIXIS_LBMAP_SHIFT       4
 162 #define PIXIS_LBMAP_ALTBANK     0x40
 163
 164 #define CONFIG_SYS_FLASH_QUIET_TEST
 165 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 166
 167 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 168 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 169 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 170 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 171
 172 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 173
 174 #if defined(CONFIG_RAMBOOT_PBL)
 175 #define CONFIG_SYS_RAMBOOT
 176 #endif
 177
 178 /* Nand Flash */
 179 #ifdef CONFIG_NAND_FSL_ELBC
 180 #define CONFIG_SYS_NAND_BASE            0xffa00000
 181 #ifdef CONFIG_PHYS_64BIT
 182 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 183 #else
 184 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 185 #endif
 186
 187 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 188 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 189 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 190
 191 /* NAND flash config */
 192 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 193                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 194                                | BR_PS_8               /* Port Size = 8 bit */ \
 195                                | BR_MS_FCM             /* MSEL = FCM */ \
 196                                | BR_V)                 /* valid */
 197 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 198                                | OR_FCM_PGS            /* Large Page*/ \
 199                                | OR_FCM_CSCT \
 200                                | OR_FCM_CST \
 201                                | OR_FCM_CHT \
 202                                | OR_FCM_SCY_1 \
 203                                | OR_FCM_TRLX \
 204                                | OR_FCM_EHTR)
 205
 206 #ifdef CONFIG_MTD_RAW_NAND
 207 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 208 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 209 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 210 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 211 #else
 212 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 213 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 214 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 215 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 216 #endif
 217 #else
 218 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 219 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 220 #endif /* CONFIG_NAND_FSL_ELBC */
 221
 222 #define CONFIG_SYS_FLASH_EMPTY_INFO
 223 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 224 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 225
 226 #define CONFIG_HWCONFIG
 227
 228 /* define to use L1 as initial stack */
 229 #define CONFIG_L1_INIT_RAM
 230 #define CONFIG_SYS_INIT_RAM_LOCK
 231 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 232 #ifdef CONFIG_PHYS_64BIT
 233 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 235 /* The assembler doesn't like typecast */
 236 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 237         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 238           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 239 #else
 240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 241 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 243 #endif
 244 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 245
 246 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 247 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 248
 249 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 250 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 251
 252 /* Serial Port - controlled on board with jumper J8
 253  * open - index 2
 254  * shorted - index 1
 255  */
 256 #define CONFIG_SYS_NS16550_SERIAL
 257 #define CONFIG_SYS_NS16550_REG_SIZE     1
 258 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 259
 260 #define CONFIG_SYS_BAUDRATE_TABLE       \
 261         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 262
 263 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 264 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 265 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 266 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 267
 268 /* I2C */
 269 #if CONFIG_IS_ENABLED(DM_I2C)
 270 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 271 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 272 #endif
 273
 274 /*
 275  * RapidIO
 276  */
 277 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 278 #ifdef CONFIG_PHYS_64BIT
 279 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 280 #else
 281 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 282 #endif
 283 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 284
 285 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 286 #ifdef CONFIG_PHYS_64BIT
 287 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 288 #else
 289 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 290 #endif
 291 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 292
 293 /*
 294  * for slave u-boot IMAGE instored in master memory space,
 295  * PHYS must be aligned based on the SIZE
 296  */
 297 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 298 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 299 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 300 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 301 /*
 302  * for slave UCODE and ENV instored in master memory space,
 303  * PHYS must be aligned based on the SIZE
 304  */
 305 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 306 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 307 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 308
 309 /* slave core release by master*/
 310 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 311 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 312
 313 /*
 314  * SRIO_PCIE_BOOT - SLAVE
 315  */
 316 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 317 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 318 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 319                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 320 #endif
 321
 322 /*
 323  * eSPI - Enhanced SPI
 324  */
 325
 326 /*
 327  * General PCI
 328  * Memory space is mapped 1-1, but I/O space must start from 0.
 329  */
 330
 331 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 332 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 333 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 334 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 335 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 336
 337 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 338 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 339 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 340 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 341 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 342
 343 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 344 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 345 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 346 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 347 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 348
 349 /* controller 4, Base address 203000 */
 350 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 351 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 352
 353 /* Qman/Bman */
 354 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 355 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 356 #ifdef CONFIG_PHYS_64BIT
 357 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 358 #else
 359 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 360 #endif
 361 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 362 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 363 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 364 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 365 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 366 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 367                                         CONFIG_SYS_BMAN_CENA_SIZE)
 368 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 369 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 370 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 371 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 372 #ifdef CONFIG_PHYS_64BIT
 373 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 374 #else
 375 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 376 #endif
 377 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 378 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 379 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 380 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 381 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 382 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 383                                         CONFIG_SYS_QMAN_CENA_SIZE)
 384 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 385 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 386
 387 #define CONFIG_SYS_DPAA_FMAN
 388 #define CONFIG_SYS_DPAA_PME
 389 /* Default address of microcode for the Linux Fman driver */
 390 #if defined(CONFIG_SPIFLASH)
 391 /*
 392  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 393  * env, so we got 0x110000.
 394  */
 395 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 396 #elif defined(CONFIG_SDCARD)
 397 /*
 398  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 399  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 400  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 401  */
 402 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 403 #elif defined(CONFIG_MTD_RAW_NAND)
 404 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 405 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 406 /*
 407  * Slave has no ucode locally, it can fetch this from remote. When implementing
 408  * in two corenet boards, slave's ucode could be stored in master's memory
 409  * space, the address can be mapped from slave TLB->slave LAW->
 410  * slave SRIO or PCIE outbound window->master inbound window->
 411  * master LAW->the ucode address in master's memory space.
 412  */
 413 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 414 #else
 415 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 416 #endif
 417 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 418 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 419
 420 #ifdef CONFIG_PCI
 421 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 422 #endif  /* CONFIG_PCI */
 423
 424 /* SATA */
 425 #ifdef CONFIG_FSL_SATA_V2
 426 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 427 #define CONFIG_SATA1
 428 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 429 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 430 #define CONFIG_SATA2
 431 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 432 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 433
 434 #define CONFIG_LBA48
 435 #endif
 436
 437 #ifdef CONFIG_FMAN_ENET
 438 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 439 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 440 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 441 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 442 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 443
 444 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 445 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 446 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 447 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 448 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 449
 450 #define CONFIG_SYS_TBIPA_VALUE  8
 451 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 452 #endif
 453
 454 /*
 455  * Environment
 456  */
 457 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 458 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 459
 460 /*
 461 * USB
 462 */
 463 #define CONFIG_HAS_FSL_DR_USB
 464 #define CONFIG_HAS_FSL_MPH_USB
 465
 466 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 467 #define CONFIG_USB_EHCI_FSL
 468 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 469 #endif
 470
 471 #ifdef CONFIG_MMC
 472 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 473 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 474 #endif
 475
 476 /*
 477  * Miscellaneous configurable options
 478  */
 479 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 480
 481 /*
 482  * For booting Linux, the board info and command line data
 483  * have to be in the first 64 MB of memory, since this is
 484  * the maximum mapped by the Linux kernel during initialization.
 485  */
 486 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 487 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 488
 489 #ifdef CONFIG_CMD_KGDB
 490 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 491 #endif
 492
 493 /*
 494  * Environment Configuration
 495  */
 496 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 497 #define CONFIG_BOOTFILE         "uImage"
 498 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 499
 500 /* default location for tftp and bootm */
 501 #define CONFIG_LOADADDR         1000000
 502
 503 #ifdef CONFIG_TARGET_P4080DS
 504 #define __USB_PHY_TYPE  ulpi
 505 #else
 506 #define __USB_PHY_TYPE  utmi
 507 #endif
 508
 509 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 510         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 511         "bank_intlv=cs0_cs1;"                                   \
 512         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 513         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 514         "netdev=eth0\0"                                         \
 515         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 516         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 517         "tftpflash=tftpboot $loadaddr $uboot && "               \
 518         "protect off $ubootaddr +$filesize && "                 \
 519         "erase $ubootaddr +$filesize && "                       \
 520         "cp.b $loadaddr $ubootaddr $filesize && "               \
 521         "protect on $ubootaddr +$filesize && "                  \
 522         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 523         "consoledev=ttyS0\0"                                    \
 524         "ramdiskaddr=2000000\0"                                 \
 525         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 526         "fdtaddr=1e00000\0"                                     \
 527         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 528         "bdev=sda3\0"
 529
 530 #define CONFIG_HDBOOT                                   \
 531         "setenv bootargs root=/dev/$bdev rw "           \
 532         "console=$consoledev,$baudrate $othbootargs;"   \
 533         "tftp $loadaddr $bootfile;"                     \
 534         "tftp $fdtaddr $fdtfile;"                       \
 535         "bootm $loadaddr - $fdtaddr"
 536
 537 #define CONFIG_NFSBOOTCOMMAND                   \
 538         "setenv bootargs root=/dev/nfs rw "     \
 539         "nfsroot=$serverip:$rootpath "          \
 540         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 541         "console=$consoledev,$baudrate $othbootargs;"   \
 542         "tftp $loadaddr $bootfile;"             \
 543         "tftp $fdtaddr $fdtfile;"               \
 544         "bootm $loadaddr - $fdtaddr"
 545
 546 #define CONFIG_RAMBOOTCOMMAND                           \
 547         "setenv bootargs root=/dev/ram rw "             \
 548         "console=$consoledev,$baudrate $othbootargs;"   \
 549         "tftp $ramdiskaddr $ramdiskfile;"               \
 550         "tftp $loadaddr $bootfile;"                     \
 551         "tftp $fdtaddr $fdtfile;"                       \
 552         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 553
 554 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 555
 556 #include <asm/fsl_secure_boot.h>
 557
 558 #endif  /* __CONFIG_H */