include/configs/colibri_pxa270.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Toradex Colibri PXA270 configuration file
   4  *
   5  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   6  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  16 /* Avoid overwriting factory configuration block */
  17 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  18
  19 /* We will never enable dcache because we have to setup MMU first */
  20 #define CONFIG_SYS_DCACHE_OFF
  21
  22 /*
  23  * Environment settings
  24  */
  25 #define CONFIG_ENV_OVERWRITE
  26 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  27 #define CONFIG_ARCH_CPU_INIT
  28 #define CONFIG_BOOTCOMMAND                                              \
  29         "if fatload mmc 0 0xa0000000 uImage; then "                     \
  30                 "bootm 0xa0000000; "                                    \
  31         "fi; "                                                          \
  32         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
  33                 "bootm 0xa0000000; "                                    \
  34         "fi; "                                                          \
  35         "bootm 0xc0000;"
  36 #define CONFIG_TIMESTAMP
  37 #define CONFIG_CMDLINE_TAG
  38 #define CONFIG_SETUP_MEMORY_TAGS
  39
  40 /*
  41  * Serial Console Configuration
  42  */
  43
  44 /*
  45  * Bootloader Components Configuration
  46  */
  47
  48 /* I2C support */
  49 #ifdef CONFIG_SYS_I2C
  50 #define CONFIG_SYS_I2C_PXA
  51 #define CONFIG_PXA_STD_I2C
  52 #define CONFIG_PXA_PWR_I2C
  53 #define CONFIG_SYS_I2C_SPEED            100000
  54 #endif
  55
  56 /* LCD support */
  57 #ifdef CONFIG_LCD
  58 #define CONFIG_PXA_LCD
  59 #define CONFIG_PXA_VGA
  60 #define CONFIG_LCD_LOGO
  61 #endif
  62
  63 /*
  64  * Networking Configuration
  65  */
  66 #ifdef  CONFIG_CMD_NET
  67
  68 #define CONFIG_DRIVER_DM9000            1
  69 #define CONFIG_DM9000_BASE              0x08000000
  70 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  71 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  72 #define CONFIG_NET_RETRY_COUNT          10
  73
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75 #endif
  76
  77 #define CONFIG_SYS_DEVICE_NULLDEV       1
  78
  79 /*
  80  * Clock Configuration
  81  */
  82 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  83
  84 /*
  85  * DRAM Map
  86  */
  87 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
  88 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  89 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  90
  91 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  92 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  93
  94 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
  95 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
  96
  97 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
  98 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  99 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 100
 101 /*
 102  * NOR FLASH
 103  */
 104 #ifdef  CONFIG_CMD_FLASH
 105 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 106 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
 107 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 108
 109 #define CONFIG_SYS_FLASH_CFI
 110 #define CONFIG_FLASH_CFI_DRIVER         1
 111 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 112
 113 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 114 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 115
 116 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
 117 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 118 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
 119 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
 120
 121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 122 #define CONFIG_SYS_FLASH_PROTECTION             1
 123 #endif
 124
 125 #define CONFIG_SYS_MONITOR_BASE         0x0
 126 #define CONFIG_SYS_MONITOR_LEN          0x40000
 127
 128 /* Skip factory configuration block */
 129 #define CONFIG_ENV_ADDR                 \
 130                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
 131 #define CONFIG_ENV_SIZE                 0x40000
 132 #define CONFIG_ENV_SECT_SIZE            0x40000
 133
 134 /*
 135  * GPIO settings
 136  */
 137 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 138 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 139 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 140 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 141
 142 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 143 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 144 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 145 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 146
 147 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 148 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 149 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 150 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 151
 152 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 153 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 154 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 155 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 156 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 157 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 158 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 159 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 160
 161 #define CONFIG_SYS_PSSR_VAL     0x30
 162
 163 /*
 164  * Clock settings
 165  */
 166 #define CONFIG_SYS_CKEN         0x00500240
 167 #define CONFIG_SYS_CCCR         0x02000290
 168
 169 /*
 170  * Memory settings
 171  */
 172 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 173 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 174 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 175 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 176 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 177 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 178 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 179 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 180
 181 /*
 182  * PCMCIA and CF Interfaces
 183  */
 184 #define CONFIG_SYS_MECR_VAL     0x00000000
 185 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 186 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 187 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 188 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 189 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 190 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 191
 192 #include "pxa-common.h"
 193
 194 #endif /* __CONFIG_H */