include/configs/colibri_pxa270.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Toradex Colibri PXA270 configuration file
   4  *
   5  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   6  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 /* Avoid overwriting factory configuration block */
  16 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  17
  18 /*
  19  * Environment settings
  20  */
  21
  22 /*
  23  * Serial Console Configuration
  24  */
  25
  26 /*
  27  * Bootloader Components Configuration
  28  */
  29
  30 /* I2C support */
  31 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  32 #define CONFIG_SYS_I2C_PXA
  33 #define CONFIG_PXA_STD_I2C
  34 #define CONFIG_PXA_PWR_I2C
  35 #endif
  36
  37 /* LCD support */
  38 #ifdef CONFIG_LCD
  39 #define CONFIG_PXA_LCD
  40 #define CONFIG_PXA_VGA
  41 #endif
  42
  43 /*
  44  * Networking Configuration
  45  */
  46 #ifdef  CONFIG_CMD_NET
  47
  48 #define CONFIG_DRIVER_DM9000            1
  49 #define CONFIG_DM9000_BASE              0x08000000
  50 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  51 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  52 #endif
  53
  54 /*
  55  * Clock Configuration
  56  */
  57 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  58
  59 /*
  60  * DRAM Map
  61  */
  62 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  63 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  64
  65 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  66 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  67
  68 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  69 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
  70
  71 /*
  72  * NOR FLASH
  73  */
  74 #ifdef  CONFIG_CMD_FLASH
  75 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
  76 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
  77 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
  78
  79 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
  80
  81 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
  82
  83 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
  84 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
  85 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
  86 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
  87 #endif
  88
  89 #define CONFIG_SYS_MONITOR_LEN          0x40000
  90
  91 /* Skip factory configuration block */
  92
  93 /*
  94  * GPIO settings
  95  */
  96 #define CONFIG_SYS_GPSR0_VAL    0x00000000
  97 #define CONFIG_SYS_GPSR1_VAL    0x00020000
  98 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
  99 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 100
 101 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 102 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 103 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 104 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 105
 106 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 107 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 108 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 109 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 110
 111 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 112 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 113 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 114 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 115 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 116 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 117 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 118 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 119
 120 #define CONFIG_SYS_PSSR_VAL     0x30
 121
 122 /*
 123  * Clock settings
 124  */
 125 #define CONFIG_SYS_CKEN         0x00500240
 126 #define CONFIG_SYS_CCCR         0x02000290
 127
 128 /*
 129  * Memory settings
 130  */
 131 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 132 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 133 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 134 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 135 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 136 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 137 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 138 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 139
 140 /*
 141  * PCMCIA and CF Interfaces
 142  */
 143 #define CONFIG_SYS_MECR_VAL     0x00000000
 144 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 145 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 146 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 147 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 148 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 149 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 150
 151 #include "pxa-common.h"
 152
 153 #endif /* __CONFIG_H */